Datasheet

39.6.1 General Control Register
Name: USBHS_CTRL
Offset: 0x0800
Reset: 0x03004000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
UIMOD UID
Access
Reset 1 1
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
USBE FRZCLK VBUSHWC
Access
Reset 0 1 0
Bit 7 6 5 4 3 2 1 0
RDERRE
Access
Reset 0
Bit 25 – UIMOD USBHS Mode
0 (HOST): The module is in USB Host mode.
1 (DEVICE): The module is in USB Device mode.
This bit can be written even if USBE = 0 or FRZCLK = 1. Disabling the USBHS (by writing a zero to the USBE bit)
does not reset this bit.
Bit 24 – UID UID Pin Enable
Must be set to ‘0’.
Bit 15 – USBE USBHS Enable
W
riting a zero to this bit resets the USBHS, disables the USB transceiver, and disables the USBHS clock inputs.
Unless explicitly stated, all registers then become read-only and are reset.
This bit can be written even if FRZCLK = 1
Value Description
0
The USBHS is disabled.
1
The USBHS is enabled.
Bit 14 – FRZCLK Freeze USB Clock
This bit can be written even if USBE = 0. Disabling the USBHS (by writing a zero to the USBE bit) does not reset this
bit, but it freezes the clock inputs whatever its value.
Value Description
0
The clock inputs are enabled.
1
The clock inputs are disabled (the resume detection is still active). This reduces the power
consumption. Unless explicitly stated, all registers then become read-only
.
Bit 8 – VBUSHWC VBUS Hardware Control
Must be set to ‘1’.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 812