Datasheet
There are two kinds of host interrupts: processing, i.e., their generation is part of the normal processing, and
exception, i.e., errors (not related to CPU exceptions).
Global Interrupts
The processing host global interrupts are:
•
Device Connection (USBHS_HSTISR.DCONNI)
• Device Disconnection (USBHS_HSTISR.DDISCI)
• USB Reset Sent (USBHS_HSTISR.RSTI)
• Downstream Resume Sent (USBHS_HSTISR.RSMEDI)
• Upstream Resume Received (USBHS_HSTISR.RXRSMI)
• Host Start of Frame (USBHS_HSTISR.HSOFI)
• Host Wakeup (USBHS_HSTISR.HWUPI)
• Pipe x (USBHS_HSTISR.PEP_x)
• DMA Channel x (USBHS_HSTISR.DMAxINT)
There is no exception host global interrupt.
Pipe Interrupts
The processing host pipe interrupts are:
• Received IN Data (USBHS_HSTPIPISRx.RXINI)
• Transmitted OUT Data (USBHS_HSTPIPISRx.TXOUTI)
• Transmitted SETUP (USBHS_HSTPIPISRx.TXSTPI)
• Short Packet (USBHS_HSTPIPISRx.SHORTPACKETI)
• Number of Busy Banks (USBHS_HSTPIPISRx.NBUSYBK)
The exception host pipe interrupts are:
• Underflow (USBHS_HSTPIPISRx.UNDERFI)
• Pipe Error (USBHS_HSTPIPISRx.PERRI)
• NAKed (USBHS_HSTPIPISRx.NAKEDI)
• Overflow (USBHS_HSTPIPISRx.OVERFI)
• Received STALLed (USBHS_HSTPIPISRx.RXSTALLDI)
• CRC Error (USBHS_HSTPIPISRx.CRCERRI)
DMA Interrupts
The processing host DMA interrupts are:
• The End of USB Transfer Status (USBHS_HSTDMASTATUSx.END_TR_ST)
• The End of Channel Buffer Status (USBHS_HSTDMASTATUSx.END_BF_ST)
• The Descriptor Loaded Status (USBHS_HSTDMASTATUSx.DESC_LDST)
There is no exception host DMA interrupt.
39.5.4 USB DMA Operation
USB packets of any length may be transferred when required by the USBHS. These transfers always feature
sequential addressing. Such characteristics mean that in case of high USBHS throughput, both AHB ports benefit
from “incrementing burst of unspecified length” since the average access latency of AHB slaves can then be reduced.
The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data transfers and channel
descriptor loading. A burst may last on the AHB busses for the duration of a whole USB packet transfer, unless
otherwise broken by the AHB arbitration or the AHB 1-Kbyte boundary crossing.
Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance
boost with paged memories. This prevents large AHB bursts from being broken in case of conflict with other AHB bus
masters, thus avoiding access latencies due to memory row changes. This means up to 128 words single cycle
unbroken AHB bursts for bulk pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/
endpoints. This maximal burst length is then controlled by the lowest programmed USB Pipe/Endpoint Size
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 772