Datasheet
The USBHS_HSTPIPISRx.RWALL bit is set when the current bank is not full, i.e., when the software can write further
data into the FIFO.
Note:
1.
If the user decides to switch to the Suspend state (by writing a zero to the USBHS_HSTCTRL.SOFE bit) while
a bank is ready to be sent, the USBHS automatically exits this state and the bank is sent.
2. In High-speed operating mode, the host controller automatically manages the PING protocol to maximize the
USB bandwidth. The user can tune the PING protocol by handling the Ping Enable (PINGEN) bit and the
bInterval Parameter for the Bulk-Out/Ping Transaction (BINTERVAL) field in USBHS_HSTPIPCFGx. See the
Host Pipe x Configuration Register for additional information.
Figure 39-21. Example of an OUT Pipe with one Data Bank
OUT
DATA
(bank 0)
ACK
HW
write data to CPU
BANK 0
SW
SW SW
SW
OUT
write data to CPU
BANK 0
USBHS_HSTPIPISRx.TXOUTI
USBHS_HSTPIPIMRx.FIFOCON
Figure 39-22. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay
OUT
DATA
(bank 0)
ACK
write data to CPU
BANK 0
SW
SW SW
SW
write data to CPU
BANK 1
SW
HW
write data to CPU
BANK0
OUT
DATA
(bank 1)
ACK
USBHS_HSTPIPISRx.TXOUTI
USBHS_HSTPIPIMRx.FIFOCON
Figure 39-23. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay
OUT
DATA
(bank 0)
ACK
write data to CPU
BANK 0
SW
SW SW
SW
OUT
DATA
(bank 1)
ACK
write data to CPU
BANK 1
SW
HW
write data to CPU
BANK0
USBHS_HSTPIPISRx.TXOUTI
USBHS_HSTPIPIMRx.FIFOCON
39.5.3.12 CRC Error
This error exists only for isochronous IN pipes. It sets the CRC Error Interrupt (USBHS_HSTPIPISRx.CRCERRI) bit,
which triggers a PEP_x interrupt if then the CRC Error Interrupt Enable (USBHS_HSTPIPIMRx.CRCERRE) bit is
one.
A CRC error can occur during IN stage if the USBHS detects a corrupted received packet. The IN packet is stored in
the bank as if no CRC error had occurred (USBHS_HSTPIPISRx.RXINI is set).
39.5.3.13 Interrupts
See the structure of the USB host interrupt system on Figure 39-3.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 771