Datasheet

The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze (USBHS_HSTPIPIMRx.PFREEZE)
field in USBHS_HSTPIPIMRx is zero).
The Received IN Data Interrupt (USBHS_HSTPIPISRx.RXINI) bit is set at the same time as the FIFO Control
(USBHS_HSTPIPIMRx.FIFOCON) bit when the current bank is full. This triggers a PEP_x interrupt if the Received IN
Data Interrupt Enable (USBHS_HSTPIPIMRx.RXINE) bit is one.
USBHS_HSTPIPISRx.RXINI is cleared by software (by writing a one to the Received IN Data Interrupt Clear bit in the
Host Pipe x Clear register (USBHS_HSTPIPIDRx.RXINIC)) to acknowledge the interrupt, which has no ef
fect on the
pipe FIFO.
The user then reads from the FIFO and clears the USBHS_HSTPIPIMRx.FIFOCON bit (by writing a one to the FIFO
Control Clear (USBHS_HSTPIPIDRx.FIFOCONC) bit) to free the bank. If the IN pipe is composed of multiple banks,
this also switches to the next bank. The USBHS_HSTPIPISRx.RXINI and USBHS_HSTPIPIMRx.FIFOCON bits are
updated in accordance with the status of the next bank.
USBHS_HSTPIPISRx.RXINI is always cleared before clearing USBHS_HSTPIPIMRx.FIFOCON.
The Read/Write Allowed (USBHS_HSTPIPISRx.RWALL) bit is set when the current bank is not empty, i.e., when the
software can read further data from the FIFO.
Figure 39-19. Example of an IN Pipe with one Data Bank
IN
DATA
(bank 0)
ACK
USBHS_HSTPIPISRx.RXINI
USBHS_HSTPIPIMRx.FIFOCON
HW
IN
DATA
(bank 0)
ACK
HW
SW
SW
SW
read data from CPU
BANK 0
read data from CPU
BANK 0
Figure 39-20. Example of an IN Pipe with two Data Banks
IN
DATA
(bank 0)
ACK
HW
IN
DATA
(bank 1)
ACK
SW
SW
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 1
USBHS_HSTPIPISRx.RXINI
USBHS_HSTPIPIMRx.FIFOCON
39.5.3.11 Management of OUT Pipes
OUT packets are sent by the host. All data which acknowledges or not the bank can be written when it is full.
The pipe must be configured and unfrozen first.
The T
ransmitted OUT Data Interrupt (USBHS_HSTPIPISRx.TXOUTI) bit is set at the same time as
USBHS_HSTPIPIMRx.FIFOCON when the current bank is free. This triggers a PEP_x interrupt if the Transmitted
OUT Data Interrupt Enable (USBHS_HSTPIPIMRx.TXOUTE) bit is one.
USBHS_HSTPIPISRx.TXOUTI is cleared by software (by writing a one to the Transmitted OUT Data Interrupt Clear
(USBHS_HSTPIPIDRx.TXOUTIC) bit to acknowledge the interrupt, which has no effect on the pipe FIFO.
The user then writes into the FIFO and clears the USBHS_HSTPIPIDRx.FIFOCON bit to allow the USBHS to send
the data. If the OUT pipe is composed of multiple banks, this also switches to the next bank. The
USBHS_HSTPIPISRx.TXOUTI and USBHS_HSTPIPIMRx.FIFOCON bits are updated in accordance with the status
of the next bank.
USBHS_HSTPIPISRx.TXOUTI is always cleared before clearing USBHS_HSTPIPIMRx.FIFOCON.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 770