Datasheet

39.5.3.4 USB Reset
The USBHS sends a USB bus reset when the user writes a one to the Send USB Reset bit in the Host General
Control register (USBHS_HSTCTRL.RESET). The USB Reset Sent Interrupt bit in the Host Global Interrupt Status
register (USBHS_HSTISR.RSTI) is set when the USB reset has been sent. In this case, all pipes are disabled and
de-allocated.
If the bus was previously in a “Suspend” state (the Start of Frame Generation Enable (USBHS_HSTCTRL.SOFE) bit
is zero), the USBHS automatically switches to the “Resume” state, the Host W
akeup Interrupt
(USBHS_HSTISR.HWUPI) bit is set and the USBHS_HSTCTRL.SOFE bit is set in order to generate SOFs or micro
SOFs immediately after the USB reset.
At the end of the reset, the user should check the USBHS_SR.SPEED field to know the speed running according to
the peripheral capability (LS.FS/HS).
39.5.3.5 Pipe Reset
A pipe can be reset at any time by writing a one to the Pipe x Reset (USBHS_HSTPIP.PRSTx) bit. This is
recommended before using a pipe upon hardware reset or when a USB bus reset has been sent. This resets:
• the internal state machine of the pipe,
• the receive and transmit bank FIFO counters,
• all the registers of the pipe (USBHS_HSTPIPCFGx, USBHS_HSTPIPISRx, USBHS_HSTPIPIMRx), except its
configuration (USBHS_HSTPIPCFGx.ALLOC, USBHS_HSTPIPCFGx.PBK, USBHS_HSTPIPCFGx.PSIZE,
USBHS_HSTPIPCFGx.PTOKEN, USBHS_HSTPIPCFGx.PTYPE, USBHS_HSTPIPCFGx.PEPNUM,
USBHS_HSTPIPCFGx.INTFRQ) and its Data Toggle Sequence field (USBHS_HSTPIPISRx.DTSEQ).
The pipe configuration remains active and the pipe is still enabled.
The pipe reset may be associated with a clear of the data toggle sequence. This can be achieved by setting the
Reset Data Toggle bit in the Pipe x Control register (USBHS_HSTPIPIMRx.RSTDT) (by writing a one to the Reset
Data Toggle Set bit in the Pipe x Control Set register (USBHS_HSTPIPIERx.RSTDTS)).
In the end, the user has to write a zero to the USBHS_HSTPIP.PRSTx bit to complete the reset operation and to start
using the FIFO.
39.5.3.6 Pipe Activation
The pipe is maintained inactive and reset (see "Pipe Reset" for more details) as long as it is disabled
(USBHS_HSTPIP.PENx = 0). The Data Toggle Sequence field (USBHS_HSTPIPISRx.DTSEQ) is also reset.
The algorithm represented in the following figure must be followed to activate a pipe.
Figure 39-18. Pipe Activation Algorithm
Pipe
Activation
USBHS_HSTPIPISRx.CFGOK == 1?
ERROR
Yes
Pipe Activated
Enable the pipe.
USBHS_HSTPIP.PENx = 1
Test if the pipe configuration is correct.
USBHS_HSTPIPPCFGx
.INTFRQ
.PEPN
UM
.PTYPE
.PTOKEN
.PSIZE
.PBK
.ALLOC
Configure the pipe:
- interrupt request frequency
- endpoint number
- type
- size
- number of banks
Allocate the configured DPRAM banks.
No
As long as the pipe is not correctly configured (USBHS_HSTPIPISRx.CFGOK = 0), the controller cannot send
packets to the device through this pipe.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 768