Datasheet

• End of Reset (USBHS_DEVISR.EORST)
•
Wakeup (USBHS_DEVISR.WAKEUP)
• End of Resume (USBHS_DEVISR.EORSM)
• Upstream Resume (USBHS_DEVISR.UPRSM)
• Endpoint x (USBHS_DEVISR.PEP_x)
• DMA Channel x (USBHS_DEVISR.DMA_x)
The exception device global interrupts are:
• Start of Frame (USBHS_DEVISR.SOF) with a frame number CRC error (USBHS_DEVFNUM.FNCERR = 1)
• Micro Start of Frame (USBHS_DEVFNUM.FNCERR.MSOF) with a CRC error
Endpoint Interrupts
The processing device endpoint interrupts are:
• Transmitted IN Data (USBHS_DEVEPTISRx.TXINI)
• Received OUT Data (USBHS_DEVEPTISRx.RXOUTI)
• Received SETUP (USBHS_DEVEPTISRx.RXSTPI)
• Short Packet (USBHS_DEVEPTISRx.SHORTPACKET)
• Number of Busy Banks (USBHS_DEVEPTISRx.NBUSYBK)
• Received OUT Isochronous Multiple Data (DTSEQ = MDATA & USBHS_DEVEPTISRx.RXOUTI)
• Received OUT Isochronous DataX (DTSEQ = DATAX & USBHS_DEVEPTISRx.RXOUTI)
The exception device endpoint interrupts are:
• Underflow (USBHS_DEVEPTISRx.UNDERFI)
• NAKed OUT (USBHS_DEVEPTISRx.NAKOUTI)
• High-Bandwidth Isochronous IN Error (USBHS_DEVEPTISRx.HBISOINERRI)
• NAKed IN (USBHS_DEVEPTISRx.NAKINI)
• High-Bandwidth Isochronous IN Flush error (USBHS_DEVEPTISRx.HBISOFLUSHI)
• Overflow (USBHS_DEVEPTISRx.OVERFI)
• STALLed (USBHS_DEVEPTISRx.STALLEDI)
• CRC Error (USBHS_DEVEPTISRx.CRCERRI)
• Transaction Error (USBHS_DEVEPTISRx.ERRORTRANS)
DMA Interrupts
The processing device DMA interrupts are:
• End of USB Transfer Status (USBHS_DEVDMASTATUSx.END_TR_ST)
• End of Channel Buffer Status (USBHS_DEVDMASTATUSx.END_BF_ST)
• Descriptor Loaded Status (USBHS_DEVDMASTATUSx.DESC_LDST)
There is no exception device DMA interrupt.
39.5.2.20 Test Modes
When written to one, the USBHS_DEVCTRL.TSTPCKT bit switches the USB device controller to a “Test-packet”
mode:
The transceiver repeatedly transmits the packet stored in the current bank. USBHS_DEVCTRL.TSTPCKT must be
written to zero to exit the Test-packet mode. The endpoint is reset by software after a Test-packet mode.
This enables the testing of rise and falling times, eye patterns, jitter, and any other dynamic waveform specifications.
The flow control used to send the packets is as follows:
• USBHS_DEVCTRL.TSTPCKT = 1;
• Store data in an endpoint bank
• Write a zero to the USBHS_DEVEPTIDRx.FIFOCON bit
To stop the Test-packet mode, write a zero to the USBHS_DEVCTRL.TSTPCKT bit.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 766