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• An underflow cannot occur during the OUT stage on a CPU action, since the user may only read if the bank is
not empty (USBHS_DEVEPTISRx.RXOUTI = 1 or USBHS_DEVEPTISRx.R
WALL = 1).
• An underflow can also occur during the OUT stage if the host sends a packet while the bank is already full.
Typically, the CPU is not fast enough. The packet is lost.
• An underflow cannot occur during the IN stage on a CPU action, since the user may only write if the bank is not
full (USBHS_DEVEPTISRx.TXINI = 1or USBHS_DEVEPTISRx.RWALL = 1).
39.5.2.15 Overflow
This error exists for all endpoint types. It sets the Overflow interrupt (USBHS_DEVEPTISRx.OVERFI) bit, which
triggers a PEP_x interrupt if the Overflow Interrupt Enable (USBHS_DEVEPTIMRx.OVERFE) bit is one.
•
An overflow can occur during the OUT stage if the host attempts to write into a bank which is too small for the
packet. The packet is acknowledged and the USBHS_DEVEPTISRx.RXOUTI bit is set as if no overflow had
occurred. The bank is filled with all the first bytes of the packet that fit in.
• An overflow cannot occur during the IN stage on a CPU action, since the user may only write if the bank is not
full (USBHS_DEVEPTISRx.TXINI = 1 or USBHS_DEVEPTISRx.RWALL = 1).
39.5.2.16 HB IsoIn Error
This error only exists for high-bandwidth isochronous IN endpoints.
At the end of the microframe, if at least one packet has been sent to the host and fewer banks than expected have
been validated (by clearing the USBHS_DEVEPTIMRx.USBHS_DEVEPTIMRx.FIFOCON) for this microframe, it sets
the USBHS_DEVEPTISRx.HBISOINERRORI bit, which triggers a PEP_x interrupt if the High Bandwidth Isochronous
IN Error Interrupt Enable (HBISOINERRORE) bit is one.
For example, if the Number of T
ransactions per MicroFrame for Isochronous Endpoint (NBTRANS) field in
USBHS_DEVEPTCFGx is three (three transactions per microframe), only two banks are filled by the CPU (three
expected) for the current microframe. Then, the HBISOINERRI interrupt is generated at the end of the microframe.
Note that an UNDERFI interrupt is also generated (with an automatic zero-length-packet), except in the case of a
missing IN token.
39.5.2.17 HB IsoFlush
This error only exists for high-bandwidth isochronous IN endpoints.
At the end of the microframe, if at least one packet has been sent to the host and there is a missing IN token during
this microframe, the bank(s) destined to this microframe is/are flushed out to ensure a good data synchronization
between the host and the device.
For example, if NBTRANS is three (three transactions per microframe) and if only the first IN token (among three) is
well received by the USBHS, the last two banks are discarded.
39.5.2.18 CRC Error
This error only exists for isochronous OUT endpoints. It sets the CRC Error Interrupt
(USBHS_DEVEPTISRx.CRCERRI) bit, which triggers a PEP_x interrupt if the CRC Error Interrupt Enable
(USBHS_DEVEPTIMRx.CRCERRE) bit is one.
A CRC error can occur during the OUT stage if the USBHS detects a corrupted received packet. The OUT packet is
stored in the bank as if no CRC error had occurred (USBHS_DEVEPTISRx.RXOUTI is set).
39.5.2.19 Interrupts
See the structure of the USB device interrupt system in Figure 39-3.
There are two kinds of device interrupts: processing, i.e., their generation is part of the normal processing, and
exception, i.e., errors (not related to CPU exceptions).
Global Interrupts
The processing device global interrupts are:
•
Suspend (USBHS_DEVISR.SUSP)
• Start of Frame (USBHS_DEVISR.SOF) interrupt with no frame number CRC error - the Frame Number CRC
Error (USBHS_DEVFNUM.FNCERR) bit is zero.
• Micro Start of Frame (USBHS_DEVISR.MSOF) with no CRC error
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
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2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 765