Datasheet

The USBHS_DEVEPTISRx.RWALL bit is set when the current bank is not empty, i.e., when the software can read
further data from the FIFO.
Figure 39-14. Example of an OUT Endpoint with one Data Bank
OUT
DATA
(bank 0)
ACK
USBHS_DEVEPTISRx.RXOUTI
USBHS_DEVEPTIMRx.FIFOCON
HW
OUT
DATA
(bank 0)
ACK
HW
SW
SW
SW
read data from CPU
BANK 0
read data from CPU
BANK 0
NAK
Figure 39-15. Example of an OUT Endpoint with two Data Banks
OUT
DATA
(bank 0)
ACK
USBHS_DEVEPTISRx.RXOUTI
USBHS_DEVEPTIMRx.FIFOCON
HW
OUT
DATA
(bank 1)
ACK
SW
SW
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 1
Detailed Description
The data is read as follows:
•
When the bank is full, USBHS_DEVEPTISRx.RXOUTI and USBHS_DEVEPTIMRx.FIFOCON are set, which
triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.RXOUTE = 1.
• The user acknowledges the interrupt by writing a one to USBHS_DEVEPTICRx.RXOUTIC in order to clear
USBHS_DEVEPTISRx.RXOUTI.
• The user can read the byte count of the current bank from USBHS_DEVEPTISRx.BYCT to know how many
bytes to read, rather than polling USBHS_DEVEPTISRx.RWALL.
• The user reads the data from the current bank by using the USBFIFOnDATA register, until all the expected data
frame is read or the bank is empty (in which case USBHS_DEVEPTISRx.RWALL is cleared and
USBHS_DEVEPTISRx.BYCT reaches zero).
• The user frees the bank and switches to the next bank (if any) by clearing USBHS_DEVEPTIMRx.FIFOCON.
If the endpoint uses several banks, the current one can be read while the following one is being written by the host.
Then, when the user clears USBHS_DEVEPTIMRx.FIFOCON, the following bank can already be read and
USBHS_DEVEPTISRx.RXOUTI is set immediately.
In High-speed mode, the PING and NYET protocols are handled by the USBHS.
• For a single bank, a NYET handshake is always sent to the host (on Bulk-out transaction) to indicate that the
current packet is acknowledged but there is no room for the next one.
• For a double bank, the USBHS responds to the OUT/DATA transaction with an ACK handshake when the
endpoint accepted the data successfully and has room for another data payload (the second bank is free).
39.5.2.14 Underflow
This error only exists for isochronous IN/OUT endpoints. It sets the Underflow Interrupt
(USBHS_DEVEPTISRx.UNDERFI) bit, which triggers a PEP_x interrupt if the Underflow Interrupt Enable
(USBHS_DEVEPTIMRx.UNDERFE) bit is one.
• An underflow can occur during the IN stage if the host attempts to read from an empty bank. A zero-length
packet is then automatically sent by the USBHS.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 764