Datasheet

The OUT retry is always ACKed. This reception sets USBHS_DEVEPTISRx.RXOUTI and
USBHS_DEVEPTISRx.TXINI. Handle this with the following software algorithm:
set TXINI
wait for RXOUTI OR TXINI
if RXOUTI, then clear bit and return
if TXINI, then continue
Once the OUT status stage has been received, the USBHS waits for a SETUP request. The SETUP request has
priority over any other request and has to be ACKed. This means that any other bit should be cleared and the FIFO
reset when a SETUP is received.
The user has to consider that the byte counter is reset when a zero-length OUT packet is received.
39.5.2.12 Management of IN Endpoints
Overview
IN packets are sent by the USB device controller upon IN requests from the host. All data which acknowledges or not
the bank can be written when it is full.
The endpoint must be configured first.
The USBHS_DEVEPTISRx.TXINI bit is set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current
bank is free. This triggers a PEP_x interrupt if the T
ransmitted IN Data Interrupt Enable
(USBHS_DEVEPTIMRx.TXINE) bit is one.
USBHS_DEVEPTISRx.TXINI is cleared by software (by writing a one to the Transmitted IN Data Interrupt Clear bit
(USBHS_DEVEPTIDRx.TXINIC) to acknowledge the interrupt, which has no effect on the endpoint FIFO.
The user then writes into the FIFO and writes a one to the FIFO Control Clear (USBHS_DEVEPTIDRx.FIFOCONC)
bit to clear the USBHS_DEVEPTIMRx.FIFOCON bit. This allows the USBHS to send the data. If the IN endpoint is
composed of multiple banks, this also switches to the next bank. The USBHS_DEVEPTISRx.TXINI and
USBHS_DEVEPTIMRx.FIFOCON bits are updated in accordance with the status of the next bank.
USBHS_DEVEPTISRx.TXINI is always cleared before clearing USBHS_DEVEPTIMRx.FIFOCON.
The USBHS_DEVEPTISRx.RWALL bit is set when the current bank is not full, i.e., when the software can write
further data into the FIFO.
Figure 39-11. Example of an IN Endpoint with one Data Bank
IN
DATA
(bank 0)
ACK
USBHS_DEVEPTISRx.TXINI
USBHS_DEVEPTIMRx.FIFOCON
HW
write data to CPU
BANK 0
SW
SW SW
SW
IN
NAK
write data to CPU
B
ANK 0
Figure 39-12. Example of an IN Endpoint with two Data Banks
IN
DATA
(bank 0)
ACK
USBHS_DEVEPTISRx.TXINI
USBHS_DEVEPTIMRx.FIFOCON
write data to CPU
BANK 0
SW
SW SW
SW
IN
DATA
(bank 1)
ACK
write data to CPU
BANK 1
SW
HW
write data to CPU
BANK0
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 762