Datasheet

Figure 39-7. Device Mode Main States
Reset
Idle
HW
USBHS_CTRL.USBE = 0
| USBHS_CTRL.UIMOD = 0
<any
other
state>
USBHS_CTRL.USBE = 0
| USBHS_CTRL.UIMOD = 0
and USBHS_CTRL.UIMOD = 1
USBHS_CTRL.USBE = 1
USBHS_HSTCTRL.RESET
| = Logical OR
& = Logic
al AND
After a hardware reset, the USBHS Device mode is in Reset state. In this state:
•
the USBHS clock is stopped to minimize power consumption (USBHS_CTRL.FRZCLK = 1),
• the internal registers of the Device mode are reset,
• the endpoint banks are de-allocated,
• neither D+ nor D- is pulled up (USBHS_DEVCTRL.DETACH = 1).
D+ or D- is pulled up according to the selected speed as soon as the USBHS_DEVCTRL.DETACH bit is written to
zero. See “Device Mode” for further details.
When the USBHS is enabled (USBHS_CTRL.USBE = 1) in Device mode (USBHS_CTRL.UIMOD = 1), its Device
mode state enters Idle state with minimal power consumption. This does not require the USB clock to be activated.
The USBHS Device mode can be disabled and reset at any time by disabling the USBHS (by writing a zero to
USBHS_CTRL.USBE) or when the Host mode is enabled (USBHS_CTRL.UIMOD = 0).
39.5.2.3 USB Reset
The USB bus reset is managed by hardware. It is initiated by a connected host.
When a USB reset is detected on the USB line, the following operations are performed by the controller:
• All endpoints are disabled, except the default control endpoint.
• The default control endpoint is reset (see 39.5.2.4 Endpoint Reset for more details).
• The data toggle sequence of the default control endpoint is cleared.
• At the end of the reset process, the End of Reset (USBHS_DEVISR.EORST) bit is set.
• During a reset, the USBHS automatically switches to High-speed mode if the host is High-speed-capable (the
reset is called High-speed reset). The user should observe the USBHS_SR.SPEED field to know the speed
running at the end of the reset (USBHS_DEVISR.EORST = 1).
39.5.2.4 Endpoint Reset
An endpoint can be reset at any time by writing a one to the Endpoint x Reset bit USBHS_DEVEPT.EPRSTx. This is
recommended before using an endpoint upon hardware reset or when a USB bus reset has been received. This
resets:
•
the internal state machine of the endpoint,
• the receive and transmit bank FIFO counters,
• all registers of this endpoint (USBHS_DEVEPTCFGx, USBHS_DEVEPTISRx, the Endpoint x Control
(USBHS_DEVEPTIMRx) register), except its configuration (USBHS_DEVEPTCFGx.ALLOC,
USBHS_DEVEPTCFGx.EPBK, USBHS_DEVEPTCFGx.EPSIZE, USBHS_DEVEPTCFGx.EPDIR,
USBHS_DEVEPTCFGx.EPTYPE) and the Data Toggle Sequence (USBHS_DEVEPTISRx.DTSEQ) field.
Note: The interrupt sources located in USBHS_DEVEPTISRx are not cleared when a USB bus reset has been
received.
The endpoint configuration remains active and the endpoint is still enabled.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 758