Datasheet

Figure 39-2. General States
Device
USBHS_CTRL.USBE = 0
USBHS_CTRL.USBE = 1
USBHS_CTRL.UIMOD = 1
Macro off:
USBHS_CTRL.USBE = 0
Clock stopped:
USBHS_CTRL.FRZCLK = 1
USBHS_CTRL_USBE = 0
HW
RESET
USBHS_CTRL.UIMOD = 0
Reset
Host
USBHS_CTRL.USBE = 1
<any
other
state>
USBHS_CTRL.USBE = 0
After a hardware reset, the USBHS is in Reset state. In this state:
•
The USBHS is disabled. The USBHS Enable bit in the General Control register (USBHS_CTRL.USBE) is zero.
• The USBHS clock is stopped in order to minimize power consumption. The Freeze USB Clock bit
(USBHS_CTRL.FRZCLK) is set.
• The UTMI is in Suspend mode.
• The internal states and registers of the Device and Host modes are reset.
• The DPRAM is not cleared and is accessible.
After writing a one to USBHS_CTRL.USBE, the USBHS enters the Device or the Host mode in idle state.
The USBHS can be disabled at any time by writing a zero to USBHS_CTRL.USBE. This acts as a hardware reset,
except that the USBHS_CTRL.FRZCLK, USBHS_CTRL.UIMOD and USBHS_DEVCTRL.LS bits are not reset.
39.5.1.2 Interrupts
One interrupt vector is assigned to the USB interface. The following figure shows the structure of the USB interrupt
system.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 753