Datasheet

39.4.2 Clocks

The clock for the USBHS bus interface is generated by the Power Management Controller. This clock can be enabled

or disabled in the Power Management Controller

. It is recommended to disable the USBHS before disabling the

clock, to avoid freezing the USBHS in an undefined state.

Before enabling the USB clock in the Power Management Controller, the USBHS must be enabled (by writing a one

to the USBHS_CTRL.USBE bit and a zero to the USBHS_CTRL.FRZCLK bit).

The USBHS can work in two modes:

• Normal mode (SPDCONF = 0) where High speed, Full speed and Low speed are available.

• Low-power mode (SPDCONF = 1) where Full speed and Low speed are available.

To ensure successful startup, follow the sequences below:

- In Normal mode:

1. Enable the USBHS peripheral clock. This is done via the register PMC_PCER.

2. Enable the USBHS (UIMOD, USBE = 1, FRZCLK = 0).

3. Enable the UPLL 480 MHz.

4. Wait for the UPLL 480 MHz to be considered as locked by the PMC.

- In Low-power mode:

1. As USB_48M must be set to 48 MHz (refer to the section “Power Management Controller (PMC)”), select

either the PLLA or the UPLL (previously set to ON), and program the PMC_USB register (source selection and

divider).

2. Enable the USBHS peripheral clock (PMC_PCER).

3. Put the USBHS in Low-power mode (SPDCONF = 1).

4. Enable the USBHS (UIMOD, USBE = 1, FRZCLK = 0).

5. Enable the USBCK bit (PMC_SCER).