Datasheet

39.3 Block Diagram
The USBHS provides a hardware device to interface a USB link to a data flow stored in a dual-port RAM (DPRAM).
In normal operation (SPDCONF = 0), the UTMI transceiver requires the UTMI PLL (480 MHz). In case of full-speed or
low-speed only
, for a lower consumption (SPDCONF = 1), the UTMI transceiver only requires 48 MHz.
Figure 39-1. USBHS Block Diagram
32 bits
System Clock
Domain
USB Clock
Domain
Rd/Wr/Ready
APB Interface
USB2.0
CORE
PEP
Alloc
AHB1
DMA
AHB0
Local
AHB
Slave
interface
Master
AHB
Multiplexer
Slave
DPRAM
UTMI
16/8 bits
APB Bus
AHB Bus
AHB Bus
PMC
HSDP/DP
HSDM/DM
ctrl
status
USB_48M Clock (needed only when SPDCONF=1)
USB_480M Clock (needed only when SPDCONF=0)
MCK
39.3.1 Signal Description
Table 39-2. Signal Description
Name Description Type
HSDM/DM HS/FS Differential Data Line - Input/Output
HSDP/DP HS/FS Differential Data Line + Input/Output
39.4 Product Dependencies
39.4.1 I/O Lines
A regular PIO line must be used to control VBUS. This is configured in the I/O Controller.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 751