Datasheet

38.8.112 GMAC Interrupt Mask Register Priority Queue x
Name: GMAC_IMRPQx
Offset: 0x0640 + (x-1)*0x04 [x=1..5]
Reset: 0x00000000
Property: Read/Write
A read of this register returns the value of the receive complete interrupt mask.
A write to this register directly af
fects the state of the corresponding bit in the Interrupt Status Register, causing an
interrupt to be generated if a '1' is written.
The following values are valid for all listed bit names of this register:
0: Corresponding interrupt is enabled.
1: Corresponding interrupt is disabled.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
HRESP ROVR
Access
Reset 0 0
Bit 7 6 5 4 3 2 1 0
TCOMP AHB RLEX RXUBR RCOMP
Access
Reset 0 0 0 0 0
Bit 11 – HRESP HRESP Not OK
Bit 10 – ROVR Receive Overrun
Bit 7 – TCOMP T
ransmit Complete
Bit 6 – AHB AHB Error
Bit 5 – RLEX Retry Limit Exceeded or Late Collision
Bit 2 – RXUBR RX Used Bit Read
Bit 1 – RCOMP Receive Complete
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 746