Datasheet

16.7 Functional Description
16.7.1 Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash Programming mode. The TST pin
integrates a permanent pulldown resistor of about 15 k
Ω to GND, so that it can be left unconnected for normal
operations. To enable Fast Flash Programming mode, refer to 18. Fast Flash Programming Interface (FFPI).
16.7.2 Debug Architecture
Figure 16-4 shows the debug architecture used. The Cortex-M7 embeds six functional units for debug:
•
Serial Wire Debug Port (SW-DP) debug access
• FPB (Flash Patch Breakpoint)
• DWT (Data Watchpoint and Trace)
• ITM (Instrumentation Trace Macrocell)
• 6-pin Embedded Trace Macrocell (ETM) for instruction trace stream, including CoreSight Trace Port Interface
Unit (TPIU)
• IEEE1149.1 JTAG Boundary scan on all digital pins
The debug architecture information that follows is mainly dedicated to developers of SW-DP Emulators/Probes and
debugging tool vendors for Cortex-M7-based microcontrollers. For further details on SW-DP, see the Cortex - M7
Technical Reference Manual.
Figure 16-4. Debug Architecture
4 Watchpoints
PC Sampler
Data Address Sampler
Data Sampler
Interrupt Trace
CPU Statistics
Data Watchpoint and Trace
6 Breakpoints
Flash Patch Breakpoint
Software Trace
32 channels
Time Stamping
Instrumentation Trace Macrocell
Serial Wire Debug
Serial Wire Debug Port
Serial Wire Output
Trace
Instruction Trace
Time Stamping
Embedded Trace Macrocell
Trace Port
16.7.3 Serial Wire Debug Port (SW-DP) Pins
The SW-DP pins SWCLK and SWDIO are commonly provided on a standard 20-pin JTAG connector defined by
ARM. For more details on voltage reference and reset state, refer to the "Signal Description" chapter
.
At startup, SW-DP pins are configured in SW-DP mode to allow connection with debugging probe.
SW-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port is
not needed in the end application. Mode selection between SW-DP mode (System I/O mode) and general I/O mode
is performed through the AHB Matrix Chip Configuration registers (CCFG_SYSIO). Configuration of the pad for
pullup, triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent
pulldown resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
The JTAG debug ports TDI, TDO, TMS and TCK are inactive. They are provided for Boundary Scan Manufacturing
Test purposes only. By default the SW-DP is active; TDO/TRACESWO can be used for trace.
SAM E70/S70/V70/V71 Family
Debug and T
est Features
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 74