Datasheet

38.8.103 GMAC Receive Buffer Queue Base Address Register Priority Queue x
Name: GMAC_RBQBAPQx
Offset: 0x0480 + (x-1)*0x04 [x=1..5]
Reset: 0x00000000
Property: Read/Write
These registers hold the start address of the receive buffer queues (receive buffers descriptor lists) for the additional
queues used when priority queues are employed.
Bit 31 30 29 28 27 26 25 24
RXBQBA[29:22]
Access
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
RXBQBA[21:14]
Access
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RXBQBA[13:6]
Access
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RXBQBA[5:0]
Access
Reset 0 0 0 0 0 0
Bits 31:2 – RXBQBA[29:0] Receive Buf
fer Queue Base Address
Holds the address of the start of the receive queue.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 736