Datasheet

16.4 Debug and Test Block Diagram

Figure 16-1. Debug and Test Block Diagram

TST

TMS/SWDIO

TCK/SWCLK

TDI

JTAGSEL

TDO/TRACESWO

Boundary

Test Access Port

(TAP)

Serial Wire Debug Port

Reset

and

Test

POR

Embedded

Trace

Macrocell

PIO

TRACED0–3

Cortex-M7

PCK3

TRACECLK

16.5 Debug and Test Pin Description

Table 16-1. Debug and Test Signal List

Signal Name Function Type Active Level

Reset/Test

NRST Microcontroller Reset Input/Output Low

TST Test Select Input –

Serial Wire Debug Port/JTAG Boundary Scan

TCK/SWCLK Test Clock/Serial Wire Clock Input –

TDI Test Data In Input –

TDO/TRACESWO Test Data Out/Trace Asynchronous Data Out Output –

TMS/SWDIO Test Mode Select/Serial Wire Input/Output Input –

JTAGSEL JTAG Selection Input High

Trace Debug Port

TRACECLK Trace Clock Output –

TRACED0–3 Trace Data Output –

SAM E70/S70/V70/V71 Family

Debug and T

est Features

echnology Inc.

Datasheet

DS60001527D-page 72