Datasheet

38.8.85 GMAC 1588 Timer Seconds Low Register
Name: GMAC_TSL
Offset: 0x1D0
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
TCS[31:24]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
TCS[23:16]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TCS[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TCS[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – TCS[31:0] T
imer Count in Seconds
This register is writable. It increments by 1 when the IEEE 1588 nanoseconds counter counts to one second. It may
also be incremented when the Timer Adjust Register is written.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
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2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 718