Datasheet

16. Debug and Test Features
16.1 Description
The device features a number of complementary debug and test capabilities. The Serial Wire Debug Port (SW-DP) is
used for standard debugging functions, such as downloading code and single-stepping through programs. It also
embeds a serial wire trace.
16.2 Embedded Characteristics
• Debug access to all memory and registers in the system, including Cortex-M register bank, when the core is
running, halted, or held in reset.
•
Serial Wire Debug Port (SW-DP) debug access
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
• Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• 6-pin Embedded Trace Macrocell (ETM) for instruction trace stream, including CoreSight
™
Trace Port Interface
Unit (TPIU)
• IEEE1149.1 JTAG Boundary scan on All Digital Pins
16.3 Associated Documents
The SAM E70/S70/V70/V71 implements the standard ARM CoreSight macrocell. For information on CoreSight, the
following reference documents are available from the ARM web site (www
.arm.com):
• Cortex-M7 User Guide Reference Manual (ARM DUI 0644)
• Cortex-M7 Technical Reference Manual (ARM DDI 0489)
• CoreSight Technology System Design Guide (ARM DGI 0012)
• CoreSight Components Technical Reference Manual (ARM DDI 0314)
• ARM Debug Interface v5 Architecture Specification (Doc. ARM IHI 0031)
• ARMv7-M Architecture Reference Manual (ARM DDI 0403)
SAM E70/S70/V70/V71 Family
Debug and T
est Features
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 71