Datasheet

38.8.59 GMAC Octets Received High Register

Name: GMAC_ORHI

Offset: 0x154

Reset: 0x00000000

Property: -

When reading the Octets Transmitted and Octets Received Registers, bits 31:0 should be read prior to bits 47:32 to

ensure reliable operation.

Bit 31 30 29 28 27 26 25 24

Access

Reset

Bit 23 22 21 20 19 18 17 16

Access

Reset

Bit 15 14 13 12 11 10 9 8

RXO[15:8]

Access

R R R R R R R R

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

RXO[7:0]

Access

R R R R R R R R

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – RXO[15:0] Received Octets

Received octets in frame without errors [47:32]. The number of octets received in valid frames of any type. This

counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is

only incremented if the frame is successfully filtered and copied to memory

SAM E70/S70/V70/V71 Family

GMAC - Ethernet MAC

echnology Inc.

Datasheet

DS60001527D-page 692