Datasheet

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Instance ID Instance Name NVIC Interrupt PMC
Clock Control
Description
60 PWM1 X X Pulse Width Modulation Controller
61 ARM FPU – ARM Floating Point Unit interrupt associated with
OFC, UFC, IOC, DZC and IDC bits.
62 SDRAMC X – SDRAM Controller
63 RSWDT X – Reinforced Safety Watchdog Timer
64 ARM CCW – ARM Cache ECC Warning
65 ARM CCF – Arm Cache ECC Fault
66 GMAC Q1 – GMAC Queue 1 Interrupt signal toggled on a
DMA write to the first word of each DMA data
buf
fer associated with queue 1.
67 GMAC Q2 – GMAC Queue 2 Interrupt signal toggled on a
DMA write to the first word of each DMA data
buffer associated with queue 2.
68 ARM IXC – Floating Point Unit Interrupt IXC associated with
FPU cumulative exception bit.
69 I2SC0 X X Inter-IC Sound Controller
70 I2SC1 X X Inter-IC Sound Controller
71 GMAC Q3 – GMAC Queue 3 Interrupt signal toggled on a
DMA write to the first word of each DMA data
buffer associated with queue 3
72 GMAC Q4 – GMAC Queue 4 Interrupt signal toggled on a
DMA write to the first word of each DMA data
buffer associated with queue 4
73 GMAC Q5 – GMAC Queue 5 Interrupt signal toggled on a
DMA write to the first word of each DMA data
buffer associated with queue 5
14.2 Peripheral Signal Multiplexing on I/O Lines
The SAM E70/S70/V70/V71 features
•
Two PIO controllers on 64-pin versions (PIOA and PIOB)
• Three PIO controllers on the 100-pin version (PIOA, PIOB and PIOD)
• Five PIO controllers on the 144-pin version (PIOA, PIOB, PIOC, PIOD and PIOE), that multiplex the I/O lines of
the peripheral set.
The SAM E70/S70/V70/V71 PIO Controllers control up to 32 lines and each line can be assigned to one of four
peripheral functions: A, B, C or D.
For more information on multiplexed signals, refer to the “Package and Pinout” chapter.
SAM E70/S70/V70/V71 Family
Peripherals
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 69