Datasheet

38.8.55 GMAC Late Collisions Register
Name: GMAC_LC
Offset: 0x144
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
LCOL[9:8]
Access
R R
Reset 0 0
Bit 7 6 5 4 3 2 1 0
LCOL[7:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 9:0 – LCOL[9:0] Late Collisions
This register counts the number of late collisions occurring after the slot time (512 bits) has expired. In 10/100 mode,
late collisions are counted twice i.e., both as a collision and a late collision.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 688