Datasheet

38.8.53 GMAC Multiple Collision Frames Register
Name: GMAC_MCF
Offset: 0x13C
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
MCOL[17:16]
Access
R R
Reset 0 0
Bit 15 14 13 12 11 10 9 8
MCOL[15:8]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MCOL[7:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 17:0 – MCOL[17:0] Multiple Collision
This register counts the number of frames experiencing between two and fifteen collisions prior to being successfully
transmitted, i.e., no underrun and not too many retries.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 686