Datasheet

38.8.28 GMAC Transmit PFC Pause Register
Name: GMAC_TPFCP
Offset: 0x0C4
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
PQ[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PEV[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 15:8 – PQ[7:0] Pause Quantum
When the Remove FCS bit in the GMAC Network Configuration register (
GMAC_NCFGR.RFCS) is written to '1', and
one or more bits in this bit field are written to '0', the associated PFC pause frame's pause quantum field value is
taken from the Transmit Pause Quantum register (GMAC_TPQ).
For each entry equal to '1' in this bit field, the pause quantum associated with that entry will be zero.
Bits 7:0 – PEV[7:0] Priority Enable Vector
When the Remove FCS bit in the GMAC Network Configuration register (GMAC_NCFGR.RFCS) is written to '1', the
priority enable vector of the PFC priority-based pause frame is set to the value stored in this bit field.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 661