Datasheet

38.8.22 GMAC Specific Address n Bottom Register
Name: GMAC_SABx
Offset: 0x88 + (x-1)*0x08 [x=1..4]
Reset: 0x00000000
Property: Read/Write
The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific
Address Register Bottom is written. They are activated when Specific Address Register T
op is written.
Bit 31 30 29 28 27 26 25 24
ADDR[31:24]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
ADDR[23:16]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
ADDR[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ADDR[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – ADDR[31:0] Specific Address n
Least significant 32 bits of the destination address, that is, bits 31:0. Bit zero indicates whether the address is
multicast or unicast and corresponds to the least significant bit of the first byte received.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 655