Datasheet

38.8.12 GMAC Interrupt Disable Register
Name: GMAC_IDR
Offset: 0x02C
Reset: –
Property: Write-only
This register is write-only and will always return zero.
The following values are valid for all listed bit names of this register:
0: No ef
fect.
1: Disables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
TSUTIMCMP WOL RXLPISBC SRI PDRSFT PDRQFT
Access
W W R W W W
Reset – – – – – –
Bit 23 22 21 20 19 18 17 16
PDRSFR PDRQFR SFT DRQFT SFR DRQFR
Access
W W W W W W
Reset – – – – – –
Bit 15 14 13 12 11 10 9 8
EXINT PFTR PTZ PFNZ HRESP ROVR
Access
W W W W W W
Reset – – – – – –
Bit 7 6 5 4 3 2 1 0
TCOMP TFC RLEX TUR TXUBR RXUBR RCOMP MFS
Access
W W W W W W W W
Reset – – – – – – – –
Bit 29 – TSUTIMCMP TSU T
imer Comparison
Bit 28 – WOL Wake On LAN
Bit 27 – RXLPISBC Receive LPI indication Status Bit Change
Receive LPI indication status bit change.
Cleared on read.
Bit 26 – SRI TSU Seconds Register Increment
Bit 25 – PDRSFT PDelay Response Frame Transmitted
Bit 24 – PDRQFT PDelay Request Frame Transmitted
Bit 23 – PDRSFR PDelay Response Frame Received
Bit 22 – PDRQFR PDelay Request Frame Received
Bit 21 – SFT PTP Sync Frame Transmitted
Bit 20 – DRQFT PTP Delay Request Frame Transmitted
Bit 19 – SFR PTP Sync Frame Received
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
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2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 642