Datasheet

38.8.5 GMAC DMA Configuration Register
Name: GMAC_DCFGR
Offset: 0x010
Reset: 0x00020004
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
DDRP
Access
Reset 0
Bit 23 22 21 20 19 18 17 16
DRBS[7:0]
Access
Reset 0 0 0 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8
TXCOEN TXPBMS RXBMS[1:0]
Access
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ESPA ESMA FBLDO[4:0]
Access
Reset 0 0 0 0 1 0 0
Bit 24 – DDRP DMA Discard Receive Packets
A write to this bit is ignored if the DMA is not configured in the packet buf
fer full store and forward mode.
Value Description
0
Received packets are stored in the SRAM based packet buffer until next AHB buffer resource becomes
available.
1
Receive packets from the receiver packet buffer memory are automatically discarded when no AHB
resource is available.
Bits 23:16 – DRBS[7:0] DMA Receive Buf
fer Size
These bits defined by these bits determines the size of buffer to use in main AHB system memory when writing
received data.
The value is defined in multiples of 64 bytes. For example:
• 0x02: 128 bytes
• 0x18: 1536 bytes (1 × max length frame/buffer)
• 0xA0: 10240 bytes (1 × 10K jumbo frame/buffer)
WARNING
Do not write 0x00 to this bit field.
Bit 11 – TXCOEN T
ransmitter Checksum Generation Offload Enable
Transmitter IP, TCP and UDP checksum generation offload enable.
Value Description
0
Frame data is unaffected.
1
The transmitter checksum generation engine calculates and substitutes checksums for transmit
frames.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 630