Datasheet

Bits 22:21 – DBW[1:0] Data Bus Width
Should always be written to '0'.
Value Name Description
0
DBW32 32-bit data bus width
1
DBW64 64-bit data bus width
Bits 20:18 – CLK[2:0] MDC Clock Division
These bits must be set according to MCK speed, and determine the number MCK will be divided by to generate
Management Data Clock (MDC). For conformance with the 802.3 specification, MDC must not exceed 2.5MHz.
Note: MDC is only active during MDIO read and write operations.
Value Name Description
0
MCK_8 MCK divided by 8 (MCK up to 20MHz)
1
MCK_16 MCK divided by 16 (MCK up to 40MHz)
2
MCK_32 MCK divided by 32 (MCK up to 80MHz)
3
MCK_48 MCK divided by 48 (MCK up to 120MHz)
4
MCK_64 MCK divided by 64 (MCK up to 160MHz)
5
MCK_96 MCK divided by 96 (MCK up to 240MHz)
Bit 17 – RFCS Remove FCS
W
riting this bit to '1' will cause received frames to be written to memory without their frame check sequence (last 4
bytes). The indicated frame length will be reduced by four bytes in this mode.
Bit 16 – LFERD Length Field Error Frame Discard
Writing a '1' to this bit discards frames with a measured length shorter than the extracted length field (as indicated by
bytes 13 and 14 in a non-VLAN tagged frame). This only applies to frames with a length field less than 0x0600.
Bits 15:14 – RXBUFO[1:0] Receive Buffer Offset
These bits determine the number of bytes by which the received data is offset from the start of the receive buffer.
Bit 13 – PEN Pause Enable
When written to '1', transmission will pause if a non-zero 802.3 classic pause frame is received and PFC has not
been negotiated.
Bit 12 – RTY Retry Test
This bit must be written to '0' for normal operation.
When writing a '1' to this bit, the back-off between collisions will always be one slot time. This setting helps testing the
too many retries condition. This setting is also useful for pause frame tests by reducing the pause counter's
decrement time from "512 bit times" to "every GRXCK cycle".
Bit 8 – MAXFS 1536 Maximum Frame Size
Writing a '1' to this bit increases the maximum accepted frame size to 1536 bytes in length. When written to '0', any
frame above 1518 bytes in length is rejected.
Bit 7 – UNIHEN Unicast Hash Enable
When writing a '1' to this bit, unicast frames will be accepted when the 6-bit hash function of the destination address
points to a bit that is set in the Hash Register.
Writing a '0' to this bit disables unicast hashing.
Bit 6 – MTIHEN Multicast Hash Enable
When writing a '1' to this bit, multicast frames will be accepted when the 6-bit hash function of the destination address
points to a bit that is set in the Hash Register.
Writing a '0' to this bit disables multicast hashing.
Bit 5 – NBC No Broadcast
Writing a '1' to this bit will reject frames addressed to the broadcast address 0xFFFFFFFFFFFF (all '1').
Writing a '0' to this bit allows broadcasting to 0xFFFFFFFFFFFF.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 626