Datasheet

38.8.1 GMAC Network Control Register
Name: GMAC_NCR
Offset: 0x000
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
FNP TXPBPF ENPBPR
Access
R/W R/W R/W
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
SRTSM TXZQPF TXPF THALT TSTART BP
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WESTAT INCSTAT CLRSTAT MPE TXEN RXEN LBL
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 18 – FNP Flush Next Packet
W
riting a '1' to this bit will flush the next packet from the external RX DPRAM. Flushing the next packet will only take
effect if the DMA is not currently writing a packet already stored in the DPRAM to memory.
Bit 17 – TXPBPF Transmit PFC Priority-based Pause Frame
Takes the values stored in the Transmit PFC Pause Register.
Bit 16 – ENPBPR Enable PFC Priority-based Pause Reception
Writing a '1' to this bit enables PFC Priority Based Pause Reception capabilities, enabling PFC negotiation and
recognition of priority-based pause frames.
Value Description
0
Normal operation
1
PFC Priority-based Pause frames are recognized.
Bit 15 – SRTSM Store Receive T
ime Stamp to Memory
Writing a '1' to this bit causes the CRC of every received frame to be replaced with the value of the nanoseconds field
of the 1588 timer that was captured as the receive frame passed the message time stamp point.
Note that bit RFCS in register GMAC_NCFGR may not be set to 1 when the timer should be captured.
Value Description
0
Normal operation
1
All received frames' CRC is replaced with a time stamp.
Bit 12 – TXZQPF T
ransmit Zero Quantum Pause Frame
Writing a '1' to this bit causes a pause frame with zero quantum to be transmitted.
Writing a '0' to this bit has no effect.
Bit 11 – TXPF Transmit Pause Frame
Writing one to this bit causes a pause frame to be transmitted.
Writing a '0' to this bit has no effect.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 622