Datasheet

• A priority enable vector taken from Transmit PFC Pause register
•
8 pause quantum registers
• Fill of 00 to take the frame to minimum frame length
• Valid FCS
The pause quantum registers used in the generated frame will depend on the trigger source for the frame as follows:
• If bit 17 of the Network Control register is written with a one, then the priority enable vector of the priority-based
pause frame will be set equal to the value stored in the Transmit PFC Pause register [7:0]. For each entry equal
to zero in the Transmit PFC Pause register [15:8], the pause quantum field of the pause frame associated with
that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit
PFC Pause register [15:8], the pause quantum associated with that entry will be zero.
• The Transmit Pause Quantum register resets to a value of 0xFFFF giving maximum pause quantum as default.
After transmission, a pause frame transmitted interrupt will be generated (bit 14 of the Interrupt Status register) and
the only statistics register that will be incremented will be the Pause Frames Transmitted register.
PFC Pause frames can also be transmitted by the MAC using normal frame transmission methods.
38.6.18 Energy Efficient Ethernet Support
Features
• Energy Efficient Ethernet according to IEEE 802.3az
• A system’s transmit path can enter a low power mode if there is nothing to transmit.
• A PHY can detect whether its link partner’s transmit path is in low power mode, and configure its own receive
path to enter low power mode.
• Link remains up during lower power mode and no frames are dropped.
• Asymmetric, one direction can be in low power mode while the other is transmitting normally.
• LPI (Low Power Idle) signaling is used to control entry and exit to and from low power modes.
Note: LPI signaling can only take place if both sides have indicated support for it through auto-negotiation.
Operation
• Low power control is done at the MII (reconciliation sublayer).
• As an architectural convenience in writing the 802.3az it is assumed that transmission is deferred by asserting
carrier sense - in practice it will not be done this way. This system will know when it has nothing to transmit and
only enter low power mode when it is not transmitting.
• LPI should not be requested unless the link has been up for at least one second.
• LPI is signaled on the MII transmit path by asserting 0x01 on txd with tx_en low and tx_er high.
• A PHY on seeing LPI requested on the MII will send the sleep signal before going quiet. After going quiet it will
periodically emit refresh signals.
• The sleep, quiet and refresh periods are defined in 802.3az, Table 78-2.
• LPI mode ends by transmitting normal idle for the wake time. There is a default time for this but it can be
adjusted in software using the Link Layer Discovery Protocol (LLDP) described in 802.3az, Clause 79.
• LPI is indicated at the receive side when sleep and refresh signaling has been detected.
38.6.19 802.1Qav Support - Credit-based Shaping
A credit-based shaping algorithm is available on the two highest priority queues and is defined in the standard
802.1Qav: Forwarding and Queuing Enhancements for Time-Sensitive Streams. This allows traffic on these queues
to be limited and to allow other queues to transmit.
Traffic shaping is enabled via the CBS (Credit Based Shaping) Control register. This enables a counter which stores
the amount of transmit 'credit', measured in bytes that a particular queue has. A queue may only transmit if it has
non-negative credit. If a queue has data to send, but is held off from doing as another queue is transmitting, then
credit will accumulate in the credit counter at the rate defined in the IdleSlope register (GMAC_CBSISQx) for that
queue.
portTransmitRate is the transmission rate, in bits per second, that the underlying MAC service that supports
transmission through the Port provides. The value of this parameter is determined by the operation of the MAC.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 600