Datasheet

The GMAC supports both hardware controlled pause of the transmitter, upon reception of a pause frame, and
hardware generated pause frame transmission.
38.6.16.1 802.3 Pause Frame Reception
Bit 13 of the Network Configuration register is the pause enable control for reception. If this bit is set, transmission will
pause if a non zero pause quantum frame is received.
If a valid pause frame is received then the Pause T
ime register is updated with the new frame's pause time,
regardless of whether a previous pause frame is active or not. An interrupt (either bit 12 or bit 13 of the Interrupt
Status register) is triggered when a pause frame is received, but only if the interrupt has been enabled (bit 12 and bit
13 of the Interrupt Mask register). Pause frames received with non zero quantum are indicated through the interrupt
bit 12 of the Interrupt Status register. Pause frames received with zero quantum are indicated on bit 13 of the
Interrupt Status register.
Once the Pause Time register is loaded and the frame currently being transmitted has been sent, no new frames are
transmitted until the pause time reaches zero. The loading of a new pause time, and hence the pausing of
transmission, only occurs when the GMAC is configured for full duplex operation. If the GMAC is configured for half
duplex there will be no transmission pause, but the pause frame received interrupt will still be triggered. A valid pause
frame is defined as having a destination address that matches either the address stored in Specific Address register
1 or if it matches the reserved address of 0x0180C2000001. It must also have the MAC control frame type ID of
0x8808 and have the pause opcode of 0x0001.
Pause frames that have frame check sequence (FCS) or other errors will be treated as invalid and will be discarded.
802.3 Pause frames that are received after Priority-based Flow Control (PFC) has been negotiated will also be
discarded. Valid pause frames received will increment the pause frames received statistic register.
The pause time register decrements every 512 bit times once transmission has stopped. For test purposes, the retry
test bit can be set (bit 12 in the Network Configuration register) which causes the Pause Time register to decrement
every GTXCK cycle once transmission has stopped.
The interrupt (bit 13 in the Interrupt Status register) is asserted whenever the Pause Time register decrements to zero
(assuming it has been enabled by bit 13 in the Interrupt Mask register). This interrupt is also set when a zero
quantum pause frame is received.
38.6.16.2 802.3 Pause Frame Transmission
Automatic transmission of pause frames is supported through the transmit pause frame bits of the Network Control
register. If either bit 11 or bit 12 of the Network Control register is written with logic 1, an 802.3 pause frame will be
transmitted, providing full duplex is selected in the Network Configuration register and the transmit block is enabled in
the Network Control register.
Pause frame transmission will happen immediately if transmit is inactive or if transmit is active between the current
frame and the next frame due to be transmitted.
Transmitted pause frames comprise the following:
• A destination address of 01-80-C2-00-00-01
• A source address taken from Specific Address register 1
• A type ID of 88-08 (MAC control frame)
• A pause opcode of 00-01
• A pause quantum register
• Fill of 00 to take the frame to minimum frame length
• Valid FCS
The pause quantum used in the generated frame will depend on the trigger source for the frame as follows:
• If bit 11 is written with a '1', the pause quantum will be taken from the Transmit Pause Quantum register. The
Transmit Pause Quantum register resets to a value of 0xFFFF giving maximum pause quantum as default.
• If bit 12 is written with a '1', the pause quantum will be zero.
After transmission, a pause frame transmitted interrupt will be generated (bit 14 of the Interrupt Status register) and
the only statistics register that will be incremented will be the Pause Frames Transmitted register.
Pause frames can also be transmitted by the MAC using normal frame transmission methods.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 598