Datasheet

38.6.11 Disable Copy of Pause Frames
Pause frames can be prevented from being written to memory by setting the disable copying of pause frames control
bit 23 in the Network Configuration register
. When set, pause frames are not copied to memory regardless of the
Copy All Frames bit, whether a hash match is found, a type ID match is identified or if a destination address match is
found.
38.6.12 VLAN Support
The following table describes an Ethernet encoded 802.1Q VLAN tag.
Table 38-5. 802.1Q VLAN Tag
TPID (Tag Protocol Identifier) 16 bits TCI (Tag Control Information) 16 bits
0x8100 First 3 bits priority, then CFI bit, last 12 bits VID
The VLAN tag is inserted at the 13th byte of the frame adding an extra four bytes to the frame. To support these extra
four bytes, the GMAC can accept frame lengths up to 1536 bytes by setting bit 8 in the Network Configuration
register
.
If the VID (VLAN identifier) is null (0x000) this indicates a priority-tagged frame.
The following bits in the receive buffer descriptor status word give information about VLAN tagged frames:-
• Bit 21 set if receive frame is VLAN tagged (i.e., type ID of 0x8100).
• Bit 20 set if receive frame is priority tagged (i.e., type ID of 0x8100 and null VID). (If bit 20 is set, bit 21 will be
set also.)
• Bit 19, 18 and 17 set to priority if bit 21 is set.
• Bit 16 set to CFI if bit 21 is set.
The GMAC can be configured to reject all frames except VLAN tagged frames by setting the discard non-VLAN
frames bit in the Network Configuration register.
38.6.13 Wake on LAN Support
The receive block supports Wake on LAN by detecting the following events on incoming receive frames:
• Magic packet
• Address Resolution Protocol (ARP) request to the device IP address
• Specific address 1 filter match
• Multicast hash filter match
These events can be individually enabled through bits [19:16] of the Wake on LAN register. Also, for Wake on LAN
detection to occur, receive enable must be set in the Network Control register, however a receive buffer does not
have to be available.
In case of an ARP request, specific address 1 or multicast filter events will occur even if the frame is errored. For
magic packet events, the frame must be correctly formed and error free.
A magic packet event is detected if all of the following are true:
• Magic packet events are enabled through bit 16 of the Wake on LAN register
• The frame's destination address matches specific address 1
• The frame is correctly formed with no errors
• The frame contains at least 6 bytes of 0xFF for synchronization
• There are 16 repetitions of the contents of Specific Address 1 register immediately following the synchronization
An ARP request event is detected if all of the following are true:
• ARP request events are enabled through bit 17 of the Wake on LAN register
• Broadcasts are allowed by bit 5 in the Network Configuration register
• The frame has a broadcast destination address (bytes 1 to 6)
• The frame has a type ID field of 0x0806 (bytes 13 and 14)
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 591