Datasheet

Each discarded frame is counted in the 10-bit length field error statistics register. Frames where the length field is
greater than or equal to 0x0600 hex will not be checked.
38.6.6 Checksum Offload for IP, TCP and UDP
The GMAC can be programmed to perform IP, TCP and UDP checksum offloading in both receive and transmit
directions, which is enabled by setting bit 24 in the Network Configuration register for receive
and bit 11 in the DMA
Configuration register for transmit.
IPv4 packets contain a 16-bit checksum field, which is the 16-bit 1’s complement of the 1’s complement sum of all 16-
bit words in the header. TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit 1’s complement of
the 1’s complement sum of all 16-bit words in the header, the data and a conceptual IP pseudo header.
To calculate these checksums in software requires each byte of the packet to be processed. For TCP and UDP this
can use a large amount of processing power. Offloading the checksum calculation to hardware can result in
significant performance improvements.
For IP, TCP or UDP checksum offload to be useful, the operating system containing the protocol stack must be aware
that this offload is available so that it can make use of the fact that the hardware can either generate or verify the
checksum.
38.6.6.1 Receiver Checksum Offload
When receive checksum offloading is enabled in the GMAC Network Configuration Register (NCFGR.RXCOEN), the
IPv4 header checksum is checked as per RFC 791, where the packet meets the following criteria:
• If present, the VLAN header must be four octets long and the CFI bit must not be set.
• Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP Encoding.
• IPv4 packet
• IP header is of a valid length
The GMAC also checks the TCP checksum as per RFC 793, or the UDP checksum as per RFC 768, if the following
criteria are met:
• IPv4 or IPv6 packet
• Good IP header checksum (if IPv4)
• No IP fragmentation
• TCP or UDP packet
When an IP, TCP or UDP frame is received, the receive buffer descriptor gives an indication if the GMAC was able to
verify the checksums. There is also an indication if the frame had SNAP encapsulation. These indication bits will
replace the type ID match indication bits when the receive checksum offload is enabled. For details of these
indication bits refer to “Receive Buffer Descriptor Entry”.
If any of the checksums are verified as incorrect by the GMAC, the packet is discarded and the appropriate statistics
counter incremented.
38.6.6.2 Transmitter Checksum Offload
The transmitter checksum offload is only available if the full store and forward mode is enabled. This is because the
complete frame to be transmitted must be read into the packet buffer memory before the checksum can be calculated
and written back into the headers at the beginning of the frame.
Transmitter checksum offload is enabled by setting bit [11] in the DMA Configuration register. When enabled, it will
monitor the frame as it is written into the transmitter packet buffer memory to automatically detect the protocol of the
frame. Protocol support is identical to the receiver checksum offload.
For transmit checksum generation and substitution to occur, the protocol of the frame must be recognized and the
frame must be provided without the FCS field, by making sure that bit [16] of the transmit descriptor word 1 is clear. If
the frame data already had the FCS field, this would be corrupted by the substitution of the new checksum fields.
If these conditions are met, the transmit checksum offload engine will calculate the IP, TCP and UDP checksums as
appropriate. Once the full packet is completely written into packet buffer memory, the checksums will be valid and the
relevant DPRAM locations will be updated for the new checksum fields as per standard IP/TCP and UDP packet
structures.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 588