Datasheet

– An enable bit Compare C, COMPCE. This bit is associated with a Screening Type 2 Compare Word 0/1

ST2CW0/1.

Each screener type has an enable bit, a match pattern and a queue number. If a received frame matches on an

enabled screening register, then the frame will be tagged with the queue value in the associated screening register,

and forwarded onto the DMA and subsequently into the external memory associated with that queue. If two screeners

are matched then the one which resides at the lowest register address will take priority so care must be taken on the

selection of the screener location.

When the priority queuing feature is enabled, the number of interrupt outputs from the GMAC core is increased to

match the number of supported queues. The number of Interrupt Status registers is increased by the same number.

Only DMA related events are reported using the individual interrupt outputs, as the GMAC can relate these events to

specific queues. All other events generated within the GMAC are reported in the interrupt associated with the lowest

priority queue. For the lowest priority queue (or the only queue when only 1 queue is selected), the Interrupt Status

addresses starting at address 0x400.

Note: The address matching is the first level of filtering. If there is a match, the screeners are the next level of

filtering for routing the data to the appropriate queue. See MAC Filtering Block for more details.

The additional screening done by the functions Compare A, B, and C each have an enable bit and compare register

field. COMPA, COMPB and COMPC in GMAC_ST2RPQ are pointers to a configured offset (OFFSVAL), value

(COMPVAL), and mask (MASKVAL). If enabled, the compare is true if the data at the offset into the frame, ANDed

with MASKVAL, is equal to the value of COMPVAL ANDed with MASKVAL. A 16-bit word comparison is done. The

byte at the offset number of bytes from the index start is compared to bits 7:0 of the configured COMPVAL and

MASKVAL. The byte at the offset number of bytes + 1 from the index start is compared to bits 15:8 of the configured

COMPVAL and MASKVAL.

The offset value in bytes, OFFSVAL, ranges from 0 to 127 bytes from either the start of the frame, the byte after the

EtherType field, the byte after the IP header (IPv4 or IPv6) or the byte after the TCP/UDP header. Note the logic to

decode the IP header or the TCP/UDP header is reused from the TCP/UDP/IP checksum offload logic and therefore

has the same restrictions on use (the main limitation is that IP fragmentation is not supported). Refer to the

Checksum Offload for IP, TCP and UDP section of this documentation for further details.

Compare A, B, and C use a common set of 24 GMAC_ST2CW0/1 registers, thus all COMPA, COMPB and COMPC

fields in the registers GMAC_ST2RPQ point to a single pool of 24 GMAC_ST2CW0/1 registers.

Note that Compare A, B and C together allow matching against an arbitrary 48 bits of data and so can be used to

match against a MAC address.

All enabled comparisons are ANDed together to form the overall type 2 screening match.