Datasheet

notification is received the frame is flushed from memory to make room for a new frame to be fetched from AHB
system memory
.
In Partial Store and Forward mode, a trigger is sent across to the MAC transmitter as soon as sufficient packet data
is available, which will then begin fetching the frame from the packet buffer memory. If, after this point, the MAC
transmitter is able to fetch data from the packet buffer faster than the AHB DMA can fill it, an underflow of the
transmitter is possible. In this case, the transmission is terminated early, and the packet buffer is completely flushed.
Transmission can only be restarted by writing a '1' to the Transmit Start bit in the Network Control register
(GMAC_NCR.TSTART).
In half duplex mode, the frame is kept in the packet buffer until notification is received from the MAC that the frame
data has either been successfully transmitted or can no longer be retransmitted (too many retries in half duplex
mode). When this notification is received the frame is flushed from memory to make room for a new frame to be
fetched from AHB system memory.
In full duplex mode, the frame is removed from the packet buffer on the fly.
Other than underflow, the only MAC related errors that can occur are due to collisions during half duplex
transmissions. When a collision occurs the frame still exists in the packet buffer memory so can be retried directly
from there. After sixteen failed transmit attempts, the frame will be flushed from the packet buffer.
38.6.3.8 Receive Packet Buffer
The receive packet buffer stores frames from the MAC receiver along with their status and statistics. Frames with
errors are flushed from the packet buffer memory, while good frames are pushed onto the DMA AHB interface.
The receiver packet buffer monitors the FIFO write interface from the MAC receiver and translates the FIFO pushes
into packet buffer writes. At the end of the received frame the status and statistics are buffered so that the information
can be used when the frame is read out. When programmed in full store and forward mode and the frame has an
error, the frame data is immediately flushed from the packet buffer memory allowing subsequent frames to utilize the
freed up space. The status and statistics for bad frames are still used to update the GMAC registers.
To accommodate the status and statistics associated with each frame, three words per packet (or two if configured in
64-bit datapath mode) are reserved at the end of the packet data. If the packet is bad and requires to be dropped, the
status and statistics are the only information held on that packet.
The receiver packet buffer will also detect a full condition so that an overflow condition can be detected. If this occurs,
subsequent packets are dropped and an RX overflow interrupt is raised.
For full store and forward, the DMA only begins packet fetches once the status and statistics for a frame are
available. If the frame has a bad status due to a frame error, the status and statistics are passed on to the GMAC
registers. If the frame has a good status, the information is used to read the frame from the packet buffer memory
and burst onto the AHB using the DMA buffer management protocol. Once the last frame data has been transferred
to the packet buffer, the status and statistics are updated to the GMAC registers.
If Partial Store and Forward mode is active, the DMA will begin fetching the packet data before the status is available.
As soon as the status becomes available, the DMA will fetch this information as soon as possible before continuing to
fetch the remainder of the frame. Once the last frame data has been transferred to the packet buffer, the status and
statistics are updated to the GMAC registers.
38.6.3.9 Priority Queuing in the DMA
The DMA by default uses a single transmit and receive queue. This means the list of transmit/receive buffer
descriptors point to data buffers associated with a single transmit/receive data stream. The GMAC can select up to 6
priority queues. Each queue has an independent list of buffer descriptors pointing to separate data streams.
The table below gives the DPRAM size associated with each queue.
Table 38-4. Queue Size
Queue Number Queue Size
5 (highest priority) 1 KB
4 2 KB
3 2 KB
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 584