Datasheet

...........continued
Bit Function
22:20 Transmit IP/TCP/UDP checksum generation offload errors:
000: No Error
.
001: The Packet was identified as a VLAN type, but the header was not fully complete, or had an error in it.
010: The Packet was identified as a SNAP type, but the header was not fully complete, or had an error in it.
011: The Packet was not of an IP type, or the IP packet was invalidly short, or the IP was not of type IPv4/
IPv6.
100: The Packet was not identified as VLAN, SNAP or IP.
101: Non supported packet fragmentation occurred. For IPv4 packets, the IP checksum was generated and
inserted.
110: Packet type detected was not TCP or UDP. TCP/UDP checksum was therefore not generated. For IPv4
packets, the IP checksum was generated and inserted.
111: A premature end of packet was detected and the TCP/UDP checksum could not be generated.
19:17 Reserved
16 No CRC to be appended by MAC. When set, this implies that the data in the buffers already contains a valid
CRC, hence no CRC or padding is to be appended to the current frame by the MAC.
This control bit must be set for the first buffer in a frame and will be ignored for the subsequent buffers of a
frame.
Note that this bit must be clear when using the transmit IP/TCP/UDP checksum generation offload,
otherwise checksum generation and substitution will not occur.
15 Last buffer, when set this bit will indicate the last buffer in the current frame has been reached.
14 Reserved
13:0 Length of buffer
To transmit frames, the buffer descriptors must be initialized by writing an appropriate Byte address to bits [31:0] of
the first word of each descriptor list entry
.
The second word of the transmit buffer descriptor is initialized with control information that indicates the length of the
frame, whether or not the MAC is to append CRC and whether the buffer is the last buffer in the frame.
After transmission the status bits are written back to the second word of the first buffer along with the used bit. Bit 31
is the used bit which must be zero when the control word is read if transmission is to take place. It is written to '1'
once the frame has been transmitted. Bits[29:20] indicate various transmit error conditions. Bit 30 is the wrap bit
which can be set for any buffer within a frame. If no wrap bit is encountered the queue pointer continues to increment.
The Transmit Buffer Queue Base Address register can only be updated while transmission is disabled or halted;
otherwise any attempted write will be ignored. When transmission is halted the transmit buffer queue pointer will
maintain its value. Therefore when transmission is restarted the next descriptor read from the queue will be from
immediately after the last successfully transmitted frame. As long as transmit is disabled by writing a '0' to the
Transmit Enable bit in the Network Control register (GMAC_NCR.TXEN), the transmit buffer queue pointer resets to
point to the address indicated by the Transmit Buffer Queue Base Address register (GMAC_TBQB).
Note: Disabling receive does not have the same effect on the receive buffer queue pointer.
Once the transmit queue is initialized, transmit is activated by writing a '1' to the Start Transmission bit of the Network
Control register (GMAC_NCR.TSTART). Transmit is halted when a buffer descriptor with its used bit set is read, a
transmit error occurs, or by writing to the Transmit Halt bit of the Network Control register (GMAC_NCR.THALT).
Transmission is suspended if a pause frame is received while the Transmit Pause Frame bit is '1' in the Network
Configuration register (GMAC_NCR.TXPF). Rewriting the Start bit (GMAC_NCR.TSTART) while transmission is
active is allowed. This is implemented by the Transmit Go variable which is readable in the Transmit Status register
(GMAC_TSR.TXGO). The TXGO variable is reset when:
• Transmit is disabled.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 581