Datasheet

In any packet buffer mode, writing a '1' to the Flush Next Package bit in the NCR register (GMAC_NCR.FNP) will
force a packet from the external SRAM-based receive packet buf
fer to be flushed. This feature is only acted upon
when the RX DMA is not currently writing packet data out to AHB, i.e., it is in an IDLE state. If the RX DMA is active,
GMAC_NCR.FNP=1 is ignored.
38.6.3.4 Transmit AHB Buffers
Frames to transmit are stored in one or more transmit AHB buffers. Transmit frames can be between 1 and 16384
Bytes long, so it is possible to transmit frames longer than the maximum length specified in the IEEE 802.3 standard.
It should be noted that zero length AHB buffers are allowed and that the maximum number of buffers permitted for
each transmit frame is 128.
The start location for each transmit AHB buffer is stored in memory in a list of transmit buffer descriptors at a location
pointed to by the transmit buffer queue pointer. The base address for this queue pointer is set in software using the
Transmit Buffer Queue Base Address register. Each list entry consists of two words. The first is the Byte address of
the transmit buffer and the second containing the transmit control and status. For the packet buffer DMA, the start
location for each AHB buffer is a Byte address, the bottom bits of the address being used to offset the start of the
data from the data-word boundary (i.e., bits 2,1 and 0 are used to offset the address for 64-bit data paths).
Frames can be transmitted with or without automatic Cyclic Redundancy Checksum (CRC) generation. If CRC is
automatically generated, pad will also be automatically generated to take frames to a minimum length of 64 Bytes.
When CRC is not automatically generated (as defined in word 1 of the transmit buffer descriptor), the frame is
assumed to be at least 64 Bytes long and pad is not generated.
An entry in the transmit buffer descriptor list is described in this table:
Table 38-3. Transmit Buffer Descriptor Entry
Bit Function
Word 0
31:0 Byte address of buffer
Word 1
31 Used—must be zero for the GMAC to read data to the transmit buffer. The GMAC sets this to one for the
first buf
fer of a frame once it has been successfully transmitted. Software must clear this bit before the buffer
can be used again.
30 Wrap—marks last descriptor in transmit buffer descriptor list. This can be set for any buffer within the frame.
29 Retry limit exceeded, transmit error detected
28 Reserved.
27 Transmit frame corruption due to AHB error—set if an error occurs while midway through reading transmit
frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during
transmission of a frame then transmission stops, FCS shall be bad and GTXER asserted).
Also set if single frame is too large for configured packet buffer memory size.
26 Late collision, transmit error detected.
25:23 Reserved
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 580