Datasheet

Each receive AHB buffer start location is a word address. The start of the first AHB buffer in a frame can be offset by
up to three Bytes, depending on the value written to bits 14 and 15 of the Network Configuration register
(GMAC_NCFGR). If the start location of the AHB buf
fer is offset, the available length of the first AHB buffer is
reduced by the corresponding number of Bytes.
To receive frames, the AHB buffer descriptors must be initialized by writing an appropriate address to bits 31:2 in the
first word of each list entry. Bit 0 must be written with zero. Bit 1 is the wrap bit and indicates the last entry in the
buffer descriptor list.
The start location of the receive buffer descriptor list must be written with the receive buffer queue base address
before reception is enabled (receive enable in the Network Control register GMAC_NCR). Once reception is enabled,
any writes to the Receive Buffer Queue Base Address register (GMAC_RBQB) are ignored. When read, it will return
the current pointer position in the descriptor list, though this is only valid and stable when receive is disabled.
If the filter block indicates that a frame should be copied to memory, the receive data DMA operation starts writing
data into the receive buffer. If an error occurs, the buffer is recovered.
An internal counter within the GMAC represents the receive buffer queue pointer and it is not visible through the CPU
interface. The receive buffer queue pointer increments by two words after each buffer has been used. It re-initializes
to the receive buffer queue base address if any descriptor has its wrap bit set.
As receive AHB buffers are used, the receive AHB buffer manager sets bit zero of the first word of the descriptor to
logic one indicating the AHB buffer has been used.
Software should search through the “used” bits in the AHB buffer descriptors to find out how many frames have been
received, checking the start of frame and end of frame bits.
When the DMA is configured in the packet buffer Partial Store And Forward mode, received frames are written out to
the AHB buffers as soon as enough frame data exists in the packet buffer. For both cases, this may mean several full
AHB buffers are used before some error conditions can be detected. If a receive error is detected the receive buffer
currently being written will be recovered. Previous buffers will not be recovered. As an example, when receiving
frames with cyclic redundancy check (CRC) errors or excessive length, it is possible that a frame fragment might be
stored in a sequence of AHB receive buffers. Software can detect this by looking for start of frame bit set in a buffer
following a buffer with no end of frame bit set.
To function properly, a 10/100 Ethernet system should have no excessive length frames or frames greater than 128
Bytes with CRC errors. Collision fragments will be less than 128 Bytes long, therefore it will be a rare occurrence to
find a frame fragment in a receive AHB buffer, when using the default value of 128 Bytes for the receive buffers size.
When in packet buffer full store and forward mode, only good received frames are written out of the DMA, so no
fragments will exist in the AHB buffers due to MAC receiver errors. There is still the possibility of fragments due to
DMA errors, for example used bit read on the second buffer of a multi-buffer frame.
If bit zero of the receive buffer descriptor is already set when the receive buffer manager reads the location of the
receive AHB buffer, the buffer has been already used and cannot be used again until software has processed the
frame and cleared bit zero. In this case, the “buffer not available” bit in the receive status register is set and an
interrupt triggered. The receive resource error statistics register is also incremented.
When the DMA is configured in the packet buffer full store and forward mode, the user can optionally select whether
received frames should be automatically discarded when no AHB buffer resource is available. This feature is selected
via the DMA Discard Receive Packets bit in the DMA Configuration register (GMAC_DCFGR.DDRP). By default, the
received frames are not automatically discarded. If this feature is off, then received packets will remain to be stored in
the SRAM-based packet buffer until AHB buffer resource next becomes available. This may lead to an eventual
packet buffer overflow if packets continue to be received when bit zero (used bit) of the receive buffer descriptor
remains set.
Note: After a used bit has been read, the receive buffer manager will re-read the location of the receive buffer
descriptor every time a new packet is received. When the DMA is not configured in the packet buffer full store and
forward mode and a used bit is read, the frame currently being received will be automatically discarded.
When the DMA is configured in the packet buffer full store and forward mode, a receive overrun condition occurs
when the receive SRAM-based packet buffer is full, or because HRESP was not OK. In all other modes, a receive
overrun condition occurs when either the AHB bus was not granted quickly enough, or because HRESP was not OK,
or because a new frame has been detected by the receive block, but the status update or write back for the previous
frame has not yet finished. For a receive overrun condition, the receive overrun interrupt is asserted and the buffer
currently being written is recovered. The next frame that is received whose address is recognized reuses the buffer.
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 579