Datasheet

• The lowest 16 bits [15:0] of the timer count sub-nanoseconds.
The 46 lower bits roll over when they have counted to 1s. The timer increments by a programmable period (to
approximately 15.2fs resolution) with each MCK period and can also be adjusted in 1ns resolution (incremented or
decremented) through APB register accesses.
38.6.3 AHB Direct Memory Access Interface
The GMAC DMA controller is connected to the MAC FIFO interface and provides a scatter-gather type capability for
packet data storage.
The DMA implements packet buffering where dual-port memories are used to buffer multiple frames.
38.6.3.1 Packet Buffer DMA
• Easier to guarantee maximum line rate due to the ability to store multiple frames in the packet buffer, where the
number of frames is limited by the amount of packet buf
fer memory and Ethernet frame size
• Full store and forward, or partial store and forward programmable options (partial store will cater for shorter
latency requirements)
• Support for Transmit TCP/IP checksum offload
• Support for priority queuing
• When a collision on the line occurs during transmission, the packet will be automatically replayed directly from
the packet buffer memory rather than having to re-fetch through the AHB (full store and forward ONLY)
• Received erroneous packets are automatically dropped before any of the packet is presented to the AHB (full
store and forward ONLY), thus reducing AHB activity
• Supports manual RX packet flush capabilities
• Optional RX packet flush when there is lack of AHB resource
38.6.3.2 Partial Store and Forward Using Packet Buffer DMA
The DMA uses SRAM-based packet buffers, and can be programmed into a low latency mode, known as Partial
Store and Forward. This mode allows for a reduced latency as the full packet is not buf
fered before forwarding.
Note: This option is only available when the device is configured for full duplex operation.
This feature is enabled via the programmable TX and RX Partial Store and Forward registers (GMAC_TPSF and
GMAC_RPSF). When the transmit Partial Store and Forward mode is activated, the transmitter will only begin to
forward the packet to the MAC when there is enough packet data stored in the packet buffer. Likewise, when the
receive Partial Store and Forward mode is activated, the receiver will only begin to forward the packet to the AHB
when enough packet data is stored in the packet buffer. The amount of packet data required to activate the
forwarding process is programmable via watermark registers. These registers are located at the same address as the
partial store and forward enable bits.
Note: The minimum operational value for the TX partial store and forward watermark is 20. There is no operational
limit for the RX partial store and forward watermark.
Enabling Partial Store and Forward is a useful means to reduce latency, but there are performance implications. The
GMAC DMA uses separate transmit and receive lists of buffer descriptors, with each descriptor describing a buffer
area in memory. This allows Ethernet packets to be broken up and scattered around the AHB memory space.
38.6.3.3 Receive AHB Buffers
Received frames, optionally including FCS, are written to receive AHB buffers stored in memory. The receive buffer
depth is programmable in the range of 64 Bytes to 16 KBytes through the DMA Configuration register
(GMAC_DCFGR), with the default being 128 Bytes.
The start location for each receive AHB buf
fer is stored in memory in a list of receive buffer descriptors at an address
location pointed to by the receive buffer queue pointer. The base address for the receive buffer queue pointer is
configured in software using the Receive Buffer Queue Base Address register (GMAC_RBQB).
Each list entry consists of two words. The first is the address of the receive AHB buffer and the second the receive
status.
If the length of a receive frame exceeds the AHB buffer length, the status word for the used buffer is written with
zeroes except for the “Start of Frame” bit, which is always set for the first buffer in a frame.
Bit zero of the address field is written to 1 to show that the buffer has been used. The receive buffer manager then
reads the location of the next receive AHB buffer and fills that with the next part of the received frame data. AHB
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 576