Datasheet

Note:
1.
Input only. GTXCK must be provided with a 25 MHz / 50 MHz external crystal oscillator for MII / RMII
interfaces, respectively.
38.5 Product Dependencies
38.5.1 I/O Lines
The pins used for interfacing the GMAC may be multiplexed with PIO lines. The programmer must first program the
PIO Controller to assign the pins to their peripheral function. If I/O lines of the GMAC are not used by the application,
they can be used for other purposes by the PIO Controller
.
38.5.2 Power Management
The GMAC is not continuously clocked. The user must first enable the GMAC clock in the Power Management
Controller before using it.
38.5.3 Interrupt Sources
The GMAC interrupt line is connected to one of the internal sources of the interrupt controller. Using the GMAC
interrupt requires prior programming of the interrupt controller
.
The GMAC features 6 interrupt sources. Refer to the table "Peripheral Identifiers" in the section "Peripherals" for the
interrupt numbers for GMAC priority queues.
Related Links
14.1 Peripheral Identifiers
38.6 Functional Description
38.6.1 Media Access Controller
The Transmit Block of the Media Access Controller (MAC) takes data from FIFO, adds preamble, checks and adds
padding and frame check sequence (FCS). Both half duplex and full duplex Ethernet modes of operation are
supported.
When operating in half duplex mode, the MAC T
ransmit Block generates data according to the Carrier Sense Multiple
Access with Collision Detect (CSMA/CD) protocol. The start of transmission is deferred if Carrier Sense (CRS) is
active. If Collision (COL) is detected during transmission, a jam sequence is asserted and the transmission is retried
after a random back off. The CRS and COL signals have no effect in full duplex mode.
The Receive Block of the MAC checks for valid preamble, FCS, alignment and length, and presents received frames
to the MAC address checking block and FIFO. Software can configure the GMAC to receive jumbo frames of up to
10240 Bytes. It can optionally strip CRC (Cyclic Redundancy Check) from the received frame before transferring it to
FIFO.
The Address Checker recognizes four specific 48-bit addresses, can recognize four different types of ID values, and
contains a 64-bit Hash register for matching multicast and unicast addresses as required. It can recognize the
broadcast address all-'1' (0xFFFFFFFFFFFF) and copy all frames. The MAC can also reject all frames that are not
VLAN tagged, and recognize Wake on LAN events.
The MAC Receive Block supports offloading of IP, TCP and UDP checksum calculations (both IPv4 and IPv6 packet
types supported), and can automatically discard bad checksum frames.
38.6.2 IEEE 1588 Time Stamp Unit
The IEEE 1588 time stamp unit (TSU) is implemented as a 94-bit timer.
•
The 48 upper bits [93:46] of the timer count seconds and are accessible in the GMAC 1588 Timer Seconds High
Register” (GMAC_TSH) and GMAC 1588 Timer Seconds Low Register (GMAC_TSL).
• The 30 lower bits [45:16] of the timer count nanoseconds and are accessible in the GMAC 1588 Timer
Nanoseconds Register (GMAC_TN).
SAM E70/S70/V70/V71 Family
GMAC - Ethernet MAC
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 575