Datasheet

37.6.22 DMA Codec Control Register
Name: ISI_DMA_C_CTRL
Offset: 0x54
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
C_DONE C_IEN C_WB C_FETCH
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 3 – C_DONE Codec T
ransfer Done
This bit is only updated in the memory.
Value Description
0
The transfer related to this descriptor has not been performed.
1
The transfer related to this descriptor has completed. This bit is updated in memory at the end of the
transfer when writeback operation is enabled.
Bit 2 – C_IEN T
ransfer Done Flag Control
Value Description
0
Codec transfer done flag generation is enabled.
1
Codec transfer done flag generation is disabled.
Bit 1 – C_WB Descriptor W
riteback Control Bit
Value Description
0
Codec channel writeback operation is disabled.
1
Codec channel writeback operation is enabled.
Bit 0 – C_FETCH Descriptor Fetch Control Bit
Value Description
0
Codec channel fetch operation is disabled.
1
Codec channel fetch operation is enabled.
SAM E70/S70/V70/V71 Family
Image Sensor Interface (ISI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 569