Datasheet

37.6.11 ISI Status Register
Name: ISI_SR
Offset: 0x28
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
FR_OVR CRC_ERR C_OVR P_OVR
Access
R R R R
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
SIP CXFR_DONE PXFR_DONE
Access
R R R
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
VSYNC CDC_PND
Access
R R
Reset 0 0
Bit 7 6 5 4 3 2 1 0
SRST DIS_DONE ENABLE
Access
R R R
Reset 0 0 0
Bit 27 – FR_OVR Frame Rate Overrun (cleared on read)
Value Description
0
No frame overrun
1
Frame overrun. The current frame is being skipped because a vsync signal has been detected while
flushing FIFOs since the last read of ISI_SR.
Bit 26 – CRC_ERR CRC Synchronization Error (cleared on read)
Value Description
0
No CRC error in the embedded synchronization frame (SAV/EAV)
1
Embedded Synchronization Correction is enabled (CRC_SYNC bit is set) in the ISI_CR and an error
has been detected and not corrected since the last read of ISI_SR. The frame is discarded and the ISI
waits for a new one.
Bit 25 – C_OVR Codec Datapath Overflow (cleared on read)
Value Description
0
No overflow
1
An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the
FIFO is full and an attempt is made to write a new sample to the FIFO since the last read of ISI_SR.
Bit 24 – P_OVR Preview Datapath Overflow (cleared on read)
Value Description
0
No overflow
1
An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the
FIFO is full and an attempt is made to write a new sample to the FIFO since the last read of ISI_SR.
Bit 19 – SIP Synchronization in Progress
When the status of the preview or codec DMA channel is modified, a minimum amount of time is required to perform
the clock domain synchronization.
SAM E70/S70/V70/V71 Family
Image Sensor Interface (ISI)
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2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 554