Datasheet

Value Description
0
No CRC correction is performed on embedded synchronization.
1
CRC correction is performed. If the correction is not possible, the current frame is discarded and the
CRC_ERR bit is set in the ISI_SR.
Bit 6 – EMB_SYNC Embedded Synchronization
Value Description
0
Synchronization by HSYNC, VSYNC.
1
Synchronization by embedded synchronization sequence SAV/EAV.
Bit 5 – GRAYLE Grayscale Little Endian
Refer to T
able 37-8 and Table 37-9 for details.
Value Description
0
The two pixels are represented in big-endian format within a 32-bit register.
1
The two pixels are represented in little-endian format within a 32-bit register.
Bit 4 – PIXCLK_POL Pixel Clock Polarity
Value Description
0
Data is sampled on rising edge of pixel clock.
1
Data is sampled on falling edge of pixel clock.
Bit 3 – VSYNC_POL V
ertical Synchronization Polarity
Value Description
0
VSYNC active high.
1
VSYNC active low.
Bit 2 – HSYNC_POL Horizontal Synchronization Polarity
Value Description
0
HSYNC active high.
1
HSYNC active low.
SAM E70/S70/V70/V71 Family
Image Sensor Interface (ISI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 542