Datasheet

11. Memories
11.1 Embedded Memories
11.1.1 Internal SRAM
SAM E70/S70/V70/V71 devices embed 384 Kbytes or 256 Kbytes of high-speed SRAM.
The SRAM is accessible over the system Cortex-M bus at address 0x2040 0000.
SAM E70/S70/V70/V71
devices embed a Multi-Port SRAM with four ports to optimize the bandwidth and latency. The
priorities, defined in the Bus Matrix for each SRAM port slave are propagated, for each request, up to the SRAM
slaves.
The Bus Matrix supports four priority levels: Normal, Bandwidth-sensitive, Latency-sensitive and Latency-critical in
order to increase the overall processor performance while securing the high-priority latency-critical requests from the
peripherals.
The SRAM controller manages interleaved addressing of SRAM blocks to minimize access latencies. It uses Bus
Matrix priorities to give the priority to the most urgent request. The less urgent request is performed no later than the
next cycle.
Two SRAM slave ports are dedicated to the Cortex-M7 while two ports are shared by the AHB masters.
11.1.2 Tightly Coupled Memory (TCM) Interface
SAM E70/S70/V70/V71 devices embed Tightly Coupled Memory (TCM) running at processor speed.
•
ITCM is a single 64-bit interface, based at 0x0000 0000 (code region).
• DTCM is composed of dual 32-bit interfaces interleaved, based at 0x2000 0000 (data region).
ITCM and DTCM are enabled/disabled in the ITCMR and DTCMR registers in ARM SCB.
DTCM is enabled by default at reset. ITCM is disabled by default at reset.
There are four TCM configurations controlled by software. When enabled, ITCM is located at 0x0000 0000,
overlapping ROM or Flash depending on the general-purpose NVM bit 1 (GPNVM). The configuration is done with
GPNVM bits [8:7].
Table 11-1. TCM Configurations in Kbytes
ITCM DTCM SRAM for 384K RAM-based SRAM for 256K RAM-based GPNVM Bits [8:7]
0 0 384 256 0
32 32 320 192 1
64 64 256 128 2
128 128 128 0 3
Accesses made to TCM regions when the relevant TCM is disabled and accesses made to the Code and SRAM
region above the TCM size limit are performed on the AHB matrix, i.e., on internal Flash or on ROM depending on
remap GPNVM bit.
Accesses made to the SRAM above the size limit will not generate aborts.
The Memory Protection Unit (MPU) can to be used to protect these areas.
11.1.3 Internal ROM
The SAM E70/S70/V70/V71 embeds an Internal ROM for the SAM Boot Assistant (SAM-BA
®
), In Application
Programming functions (IAP) and Fast Flash Programming Interface (FFPI).
At any time, the ROM is mapped at address 0x0080 0000.
SAM E70/S70/V70/V71 Family
Memories
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 54