Datasheet

37.5 Functional Description
The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors
and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus.
This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock. The
reduced pin count alternative for synchronization is supported for sensors that embed SA
V (start of active video) and
EAV (end of active video) delimiters in the data stream.
The Image Sensor Interface interrupt line is connected to the Advanced Interrupt Controller and can trigger an
interrupt at the beginning of each frame and at the end of a DMA frame transfer. If the SAV/EAV synchronization is
used, an interrupt can be triggered on each delimiter event.
For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr 4:2:2, RGB 8:8:8, RGB
5:6:5 and may be processed before the storage in memory. When the preview DMA channel is configured and
enabled, the preview path is activated and an ‘RGB frame’ is moved to memory. The preview path frame rate is
configured with the FRATE field of the ISI_CFG1 register. When the codec DMA channel is configured and enabled,
the codec path is activated and a ‘YCbCr 4:2:2 frame’ is captured as soon as the ISI_CDC bit of the ISI Control
Register (ISI_CR) is set.
When the FULL bit of the ISI_CFG1 register is set, both preview DMA channel and codec DMA channel can operate
simultaneously. When a zero is written to the FULL bit of the ISI_CFG1 register, a hardware scheduler checks the
FRATE field. If its value is zero, a preview frame is skipped and a codec frame is moved to memory instead. If its
value is other than zero, at least one free frame slot is available. The scheduler postpones the codec frame to that
free available frame slot.
The data stream may be sent on both preview path and codec path if the value of bit ISI_CDC in the ISI_CR is one.
To optimize the bandwidth, the codec path should be enabled only when a capture is required.
In Grayscale mode, the input data stream is stored in memory without any processing. The 12-bit data, which
represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the
GS_MODE bit in the ISI_CFG2 register. The codec datapath is not available when grayscale image is selected.
A frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames.
37.5.1 Data Timing
37.5.1.1 VSYNC/HSYNC Data Timing
In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the pixel clock (ISI_PCK),
after SFD lines of vertical blanking and SLD pixel clock periods delay programmed in the ISI_CR.
The data timing using horizontal and vertical synchronization are shown in the following figure.
Figure 37-3. HSYNC and VSYNC Synchronization
ISI_VSYNC
ISI_HSYNC
ISI_PCK
Frame
1 line
Y Cb Y Cr Y Cb Y Cr Y Cb Y CrISI_DATA[7..0]
37.5.1.2 SAV/EAV Data Timing
The ITU-RBT.656-4 standard defines the functional timing for an 8-bit wide interface.
SAM E70/S70/V70/V71 Family
Image Sensor Interface (ISI)
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2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 530