Datasheet

36.9.29 XDMAC Channel x Data Stride Memory Set Pattern Register [x = 0..23]
Name: XDMAC_CDS_MSP
Offset: 0x7C + n*0x40 [n=0..23]
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
DDS_MSP[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DDS_MSP[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SDS_MSP[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SDS_MSP[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 31:16 – DDS_MSP[15:0] Channel x Destination Data Stride or Memory Set Pattern
When XDMAC_CCx.MEMSET = 0, this field indicates the destination data stride.
When XDMAC_CCx.MEMSET = 1, this field indicates the memory set pattern.
Bits 15:0 – SDS_MSP[15:0]
Channel x Source Data stride or Memory Set Pattern
When XDMAC_CCx.MEMSET = 0, this field indicates the source data stride.
When XDMAC_CCx.MEMSET = 1, this field indicates the memory set pattern.
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 525