Datasheet
36.9.28 XDMAC Channel x Configuration Register [x = 0..23]
Name: XDMAC_CC
Offset: 0x78 + n*0x40 [n=0..23]
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
PERID[6:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
WRIP RDIP INITD DAM[1:0] SAM[1:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DIF SIF DWIDTH[1:0] CSIZE[2:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 30:24 – PERID[6:0] Channel x Peripheral Hardware Request Line Identifier
This field contains the peripheral hardware request line identifier
. PERID refers to identifiers defined in “DMA
Controller Peripheral Connections”.
Bit 23 – WRIP Write in Progress (this bit is read-only)
0 (DONE): No active write transaction on the bus.
1 (IN_PROGRESS): A write transaction is in progress.
Bit 22 – RDIP Read in Progress (this bit is read-only)
0 (DONE): No active read transaction on the bus.
1 (IN_PROGRESS): A read transaction is in progress.
Bit 21 – INITD Channel Initialization Done (this bit is read-only)
0 (IN_PROGRESS): Channel initialization is in progress.
1 (TERMINATED): Channel initialization is completed.
Note: When set to 0, XDMAC_CUBC.UBLEN and XDMAC_CNDA.NDA field values are unreliable each time a
descriptor is being updated. See 36.8 XDMAC Software Requirements.
Bits 19:18 – DAM[1:0] Channel x Destination Addressing Mode
Value Name Description
0
FIXED_AM The address remains unchanged.
1
INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size).
2
UBS_AM The microblock stride is added at the microblock boundary.
3
UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is
added at the data boundary
.
Bits 17:16 – SAM[1:0] Channel x Source Addressing Mode
Value Name Description
0
FIXED_AM The address remains unchanged.
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 523