Datasheet

9. Interconnect
The system architecture is based on the ARM Cortex-M7 processor connected to the main AHB Bus Matrix, the
embedded Flash, the multi-port SRAM and the ROM.
The 32-bit AHBP interface is a single 32-bit wide interface that accesses the peripherals connected on the main Bus
Matrix. It is used only for data access. Instruction fetches are never performed on the AHBP interface. The bus,
AHBP or AXIM, accessing the peripheral memory area [0x40000000 to 0x60000000] is selected in the AHBP control
register
.
The 32-bit AHBS interface provides system access to the ITCM, D1TCM, and D0TCM. It is connected on the main
Bus Matrix and allows the XDMA to transfer from memory or peripherals to the instruction or data TCMs.
The 64-bit AXIM interface is a single 64-bit wide interface connected through two ports of the AXI Bridge to the main
AHB Bus Matrix and to two ports of the multi-port SRAM. The AXIM interface allows:
• Instruction fetches
• Data cache linefills and evictions
• Non-cacheable normal-type memory data accesses
• Device and strongly-ordered type data accesses, generally to peripherals
The interleaved multi-port SRAM optimizes the Cortex-M7 accesses to the internal SRAM.
The interconnect of the other masters and slaves is described in 19. Bus Matrix (MATRIX).
The figure below shows the connections of the different Cortex-M7 ports.
Figure 9-1. Interconnect Block Diagram
12-layer AHB Bus Matrix
f
MAX
150
MHz
In-Circuit Emulator
MPU
Cortex-M7 Processor
f
MAX
300 MHz
NVIC
FPU
TPIU
ETM
16 Kbytes
ICache + ECC
16 Kbytes
DCache + ECC
TCM
Interface
S S S
M
MM S
AXIM
AHBP
S
AHBS
AXI Bridge
ROM
Multi-Port SRAM
Flash
ITCM
DTCM
TCM SRAM
System SRAM
64-bit
32-bit
32-bit
2 x 32-bit
64-bit
32-bit32-bit
32-bit 32-bit
SAM E70/S70/V70/V71 Family
Interconnect
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 52