Datasheet

36.9.24 XDMAC Channel x Next Descriptor Address Register [x = 0..23]
Name: XDMAC_CNDA
Offset: 0x68 + n*0x40 [n=0..23]
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
NDA[29:22]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
NDA[21:14]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
NDA[13:6]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
NDA[5:0] NDAIF
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bits 31:2 – NDA[29:0] Channel x Next Descriptor Address
The 30-bit width of the NDA field represents the next descriptor address range 31:2. The descriptor is word-aligned
and the two least significant register bits 1:0 are ignored.
Bit 0 – NDAIF Channel x Next Descriptor Interface
Value Description
0
The channel descriptor is retrieved through system interface 0.
1
The channel descriptor is retrieved through system interface 1.
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 519