Datasheet

36.9.22 XDMAC Channel x Source Address Register [x = 0..23]
Name: XDMAC_CSA
Offset: 0x60 + n*0x40 [n=0..23]
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
SA[31:24]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
SA[23:16]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SA[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SA[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – SA[31:0] Channel x Source Address
Program this register with the source address of the DMA transfer
.
A configuration error is generated when this address is not aligned with the transfer data size.
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 517